CSSELR_EL1 Cache Size Selection Register when FEAT_AA64 is implemented CSSELR Architectural AArch32 31 0 31 0 31 0 31 0 Selects the current Cache Size ID Register, CCSIDR_EL1, by specifying the required cache level and the cache type (either instruction or data cache). Identification Registers CSSELR_EL1 is a 64-bit register. 63 5 63:5 Reserved, RES0. TnD 4 4 0 Allocation Tag not Data bit. When CSSELR_EL1.InD == 1, this bit is RES0. If CSSELR_EL1.{TnD, Level, InD} is programmed to a cache level that is not implemented, then the value for this field on a read of CSSELR_EL1 is UNKNOWN. 0b0 Data, Instruction or Unified cache. 0b1 Separate Allocation Tag cache. AU When FEAT_MTE2 is implemented 4 4 4 Reserved, RES0. Otherwise Level 3 1 3:1 Cache level of required cache. All other values are reserved. If CSSELR_EL1.{TnD, Level, InD} is programmed to a cache level that is not implemented, then the value for this field on a read of CSSELR_EL1 is UNKNOWN. 0b000 Level 1 cache. 0b001 Level 2 cache. 0b010 Level 3 cache. 0b011 Level 4 cache. 0b100 Level 5 cache. 0b101 Level 6 cache. 0b110 Level 7 cache. AU InD 0 0 0 Instruction not Data bit. If CSSELR_EL1.{TnD, Level, InD} is programmed to a cache level that is not implemented, then a read of CSSELR_EL1 is CONSTRAINED UNPREDICTABLE, and returns UNKNOWN values for CSSELR_EL1.{Level, InD}. 0b0 Data or unified cache. 0b1 Instruction cache. AU MRS <Xt>, CSSELR_EL1 if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TID2 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_EVT) && HCR_EL2().TID4 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().CSSELR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = CSSELR_EL1(); end; elsif PSTATE.EL == EL2 then X{64}(t) = CSSELR_EL1(); elsif PSTATE.EL == EL3 then X{64}(t) = CSSELR_EL1(); end; MSR CSSELR_EL1, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TID2 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_EVT) && HCR_EL2().TID4 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().CSSELR_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else CSSELR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then CSSELR_EL1() = X{64}(t); elsif PSTATE.EL == EL3 then CSSELR_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel