DACR32_EL2 Domain Access Control Register when FEAT_AA32EL1 is implemented and FEAT_AA64 is implemented DACR Architectural AArch32 31 0 31 0 31 0 31 0 Allows access to the AArch32 DACR register from AArch64 state only. Its value has no effect on execution in AArch64 state. Memory If EL2 is not implemented but EL3 is implemented, and EL1 is capable of using AArch32, then this register is not RES0. DACR32_EL2 is a 64-bit register. 63 32 63:32 Reserved, RES0. D<n> 31 0 31:0 Domain n access permission, where n = 0 to 15. Permitted values are: The value 0b10 is reserved. 15 0 0b00 No access. Any access to the domain generates a Domain fault. 0b01 Client. Accesses are checked against the permission bits in the translation tables. 0b11 Manager. Accesses are not checked against the permission bits in the translation tables. AU MRS <Xt>, DACR32_EL2 if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = DACR32_EL2(); elsif PSTATE.EL == EL3 then X{64}(t) = DACR32_EL2(); end; MSR DACR32_EL2, <Xt> if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then DACR32_EL2() = X{64}(t); elsif PSTATE.EL == EL3 then DACR32_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel