DAIF Interrupt Mask Bits when FEAT_AA64 is implemented Allows access to the interrupt mask bits. PSTATE DAIF is a 64-bit register. 63 10 63:10 Reserved, RES0. D 9 9 9 Process state D mask. When the target Exception level of the debug exception is higher than the current Exception level, the exception is not masked by this bit. 0b0 Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception level are not masked. 0b1 Watchpoint, Breakpoint, and Software Step exceptions targeted at the current Exception level are masked. '1' A 8 8 8 SError exception mask bit. 0b0 Exception not masked. 0b1 Exception masked. '1' I 7 7 7 IRQ mask bit. 0b0 Exception not masked. 0b1 Exception masked. '1' F 6 6 6 FIQ mask bit. 0b0 Exception not masked. 0b1 Exception masked. '1' 5 0 5:0 Reserved, RES0. MRS <Xt>, DAIF if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then if ELIsInHost(EL0) || SCTLR_EL1().UMA == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else X{64}(t) = Zeros{54} :: PSTATE.[D,A,I,F] :: Zeros{6}; end; elsif PSTATE.EL == EL1 then X{64}(t) = Zeros{54} :: PSTATE.[D,A,I,F] :: Zeros{6}; elsif PSTATE.EL == EL2 then X{64}(t) = Zeros{54} :: PSTATE.[D,A,I,F] :: Zeros{6}; elsif PSTATE.EL == EL3 then X{64}(t) = Zeros{54} :: PSTATE.[D,A,I,F] :: Zeros{6}; end; MSR DAIF, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then if ELIsInHost(EL0) || SCTLR_EL1().UMA == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; else PSTATE.[D,A,I,F] = X{64}(t)[9:6]; end; elsif PSTATE.EL == EL1 then PSTATE.[D,A,I,F] = X{64}(t)[9:6]; elsif PSTATE.EL == EL2 then PSTATE.[D,A,I,F] = X{64}(t)[9:6]; elsif PSTATE.EL == EL3 then PSTATE.[D,A,I,F] = X{64}(t)[9:6]; end; MSR DAIFSet, #<imm> MSR DAIFClr, #<imm> 2026-03-26 20:27:25 2026-03_rel