DBGDTR_EL0 Debug Data Transfer Register, half-duplex when FEAT_AA64 is implemented DBGDTRRXint Architectural AArch32 63 32 31 0 63 32 31 0 when written DBGDTRRX_EL0 Architectural External 63 32 31 0 63 32 31 0 when written DBGDTRRX_EL0 Architectural AArch64 63 32 31 0 63 32 31 0 when written DBGDTRTXint Architectural AArch32 31 0 31 0 31 0 31 0 when written DBGDTRTX_EL0 Architectural External 31 0 31 0 31 0 31 0 when written DBGDTRTX_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 when written DBGDTRTXint Architectural AArch32 63 32 31 0 63 32 31 0 when read DBGDTRTX_EL0 Architectural External 63 32 31 0 63 32 31 0 when read DBGDTRTX_EL0 Architectural AArch64 63 32 31 0 63 32 31 0 when read DBGDTRRXint Architectural AArch32 31 0 31 0 31 0 31 0 when read DBGDTRRX_EL0 Architectural External 31 0 31 0 31 0 31 0 when read DBGDTRRX_EL0 Architectural AArch64 31 0 31 0 31 0 31 0 when read Transfers 64 bits of data between the PE and an external debugger. Can transfer both ways using only a single register. Debug DBGDTR_EL0 is a 64-bit register. HighWord 63 32 63:32 If TXfull is 1, then writes to this register set DTRRX to an UNKNOWN value. Otherwise, writes to this register set DTRRX to the value in this field. Writes to this register do not change RXfull. Reads of this register: If RXfull is 1, return the last value written to DTRTX. If RXfull is 0, return an UNKNOWN value. After the read, RXfull is cleared to 0. LowWord 31 0 31:0 If TXfull is 1, then writes to this register set DTRTX to an UNKNOWN value. Otherwise, writes to this register set DTRTX to the value in this field and set TXfull to 1. Reads of this register: If RXfull is 1, return the last value written to DTRRX. If RXfull is 0, return an UNKNOWN value. After the read, RXfull is cleared to 0. MRS <Xt>, DBGDTR_EL0 if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif Halted() then X{64}(t) = Read_DBGDTR_EL0{64}(); elsif PSTATE.EL == EL0 then if MDSCR_EL1().TDCC == '1' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (HCR_EL2().TGE == '1' || MDCR_EL2().[TDE,TDA] != '00') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = Read_DBGDTR_EL0{64}(); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().[TDE,TDA] != '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = Read_DBGDTR_EL0{64}(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = Read_DBGDTR_EL0{64}(); end; elsif PSTATE.EL == EL3 then X{64}(t) = Read_DBGDTR_EL0{64}(); end; MSR DBGDTR_EL0, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif Halted() then Write_DBGDTR_EL0{64}(X{64}(t)); elsif PSTATE.EL == EL0 then if MDSCR_EL1().TDCC == '1' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && (HCR_EL2().TGE == '1' || MDCR_EL2().[TDE,TDA] != '00') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else Write_DBGDTR_EL0{64}(X{64}(t)); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && MDCR_EL2().TDCC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().[TDE,TDA] != '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else Write_DBGDTR_EL0{64}(X{64}(t)); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && IsFeatureImplemented(FEAT_FGT) && MDCR_EL3().TDCC == '1' then AArch64_SystemAccessTrap(EL3, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then AArch64_SystemAccessTrap(EL3, 0x18); else Write_DBGDTR_EL0{64}(X{64}(t)); end; elsif PSTATE.EL == EL3 then Write_DBGDTR_EL0{64}(X{64}(t)); end; 2026-03-26 20:27:25 2026-03_rel