DBGVCR32_EL2 Debug Vector Catch Register when FEAT_AA32EL1 is implemented and FEAT_AA64 is implemented DBGVCR Architectural AArch32 31 0 31 0 31 0 31 0 Allows access to the AArch32 register DBGVCR from AArch64 state only. Its value has no effect on execution in AArch64 state. Debug If EL2 is not implemented but EL3 is implemented, and EL1 is capable of using AArch32, then this register is not RES0. DBGVCR32_EL2 is a 64-bit register. When EL3 is implemented EL3 is implemented and using AArch64 63 32 63:32 Reserved, RES0. NSF 31 31 31 FIQ vector catch enable in Non-secure state. The exception vector offset is 0x1C. AU NSI 30 30 30 IRQ vector catch enable in Non-secure state. The exception vector offset is 0x18. AU 29 29 29 Reserved, RES0. NSD 28 28 28 Data Abort exception vector catch enable in Non-secure state. The exception vector offset is 0x10. AU NSP 27 27 27 Prefetch Abort vector catch enable in Non-secure state. The exception vector offset is 0x0C. AU NSS 26 26 26 Supervisor Call (SVC) vector catch enable in Non-secure state. The exception vector offset is 0x08. AU NSU 25 25 25 Undefined Instruction vector catch enable in Non-secure state. The exception vector offset is 0x04. AU 24 8 24:8 Reserved, RES0. SF 7 7 7 FIQ vector catch enable in Secure state. The exception vector offset is 0x1C. AU SI 6 6 6 IRQ vector catch enable in Secure state. The exception vector offset is 0x18. AU 5 5 5 Reserved, RES0. SD 4 4 4 Data Abort exception vector catch enable in Secure state. The exception vector offset is 0x10. AU SP 3 3 3 Prefetch Abort vector catch enable in Secure state. The exception vector offset is 0x0C. AU SS 2 2 2 Supervisor Call (SVC) vector catch enable in Secure state. The exception vector offset is 0x08. AU SU 1 1 1 Undefined Instruction vector catch enable in Secure state. The exception vector offset is 0x04. AU 0 0 0 Reserved, RES0. When EL3 is not implemented EL3 is not implemented 63 8 63:8 Reserved, RES0. F 7 7 7 FIQ vector catch enable. The exception vector offset is 0x1C. AU I 6 6 6 IRQ vector catch enable. The exception vector offset is 0x18. AU 5 5 5 Reserved, RES0. D 4 4 4 Data Abort exception vector catch enable. The exception vector offset is 0x10. AU P 3 3 3 Prefetch Abort vector catch enable. The exception vector offset 0x0C. AU S 2 2 2 Supervisor Call (SVC) vector catch enable. The exception vector offset is 0x08. AU U 1 1 1 Undefined Instruction vector catch enable. The exception vector offset is 0x04. AU 0 0 0 Reserved, RES0. When EL3 is implemented When EL3 is not implemented MRS <Xt>, DBGVCR32_EL2 if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDA == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = DBGVCR32_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = DBGVCR32_EL2(); end; MSR DBGVCR32_EL2, <Xt> if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDA == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else DBGVCR32_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then DBGVCR32_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel