DBGWVR<n>_EL1 Debug Watchpoint Value Registers when FEAT_AA64 is implemented 0 63 DBGWVR<n> Architectural AArch32 31 0 31 0 31 0 31 0 DBGWVR<n>_EL1 Architectural External 63 0 63 0 63 0 63 0 Holds a data address value for use in watchpoint matching. Forms watchpoint n together with control register DBGWCR<n>_EL1. Debug If watchpoint n is not implemented then accesses to this register are UNDEFINED. DBGWVR<n>_EL1 is a 64-bit register. RESS[14:8] 63 57 63:57 Reserved, Sign extended. Software must set all bits in this field to the same value as the most significant bit of the VA field. If all bits in this field are not the same value as the most significant bit of the VA field, then all of the following apply: It is CONSTRAINED UNPREDICTABLE whether the PE ignores this field when comparing an address. It is IMPLEMENTATION DEFINED whether the value read back in each bit of this field is a copy of the most significant bit of the VA field or the value written. VA[56:53] 56 53 3:0 Extension to VA[48:2]. For more information, see VA[48:2]. AU When FEAT_LVA3 is implemented RESS[7:4] 56 53 3:0 Extension to RESS[14:8]. For more information, see RESS[14:8]. Otherwise VA[52:49] 52 49 3:0 Extension to VA[48:2]. For more information, see VA[48:2]. AU When FEAT_LVA is implemented RESS[3:0] 52 49 3:0 Extension to RESS[14:8]. For more information, see RESS[14:8]. Otherwise VA[48:2] 48 2 48:2 Bits[48:2] of the address value for comparison. When FEAT_LVA3 is implemented, (VA[56:53]:VA[52:49]) forms the upper part of the address value. If FEAT_LVA3 is not implemented, bits VA[56:53] are part of the RESS field. When FEAT_LVA is implemented, VA[52:49] forms the upper part of the address value. If FEAT_LVA is not implemented, bits [52:49] are part of the RESS field. Arm deprecates setting DBGWVR<n>_EL1[2] == 1. AU 1 0 1:0 Reserved, RES0. When FEAT_Debugv8p9 is implemented, a PE is permitted to support up to 64 implemented watchpoints. 0-15 MRS <Xt>, DBGWVR<m>_EL1 let m:integer = UInt(CRm[3:0]); if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif (!IsFeatureImplemented(FEAT_Debugv8p9) && m >= NUM_WATCHPOINTS) || (IsFeatureImplemented(FEAT_Debugv8p9) && m + (UInt(MDSELR_EL1().BANK) * 16) >= NUM_WATCHPOINTS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDA == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGRTR_EL2().DBGWVRn_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().[TDE,TDA] != '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then Halt(DebugHalt_SoftwareAccess); else if IsFeatureImplemented(FEAT_Debugv8p9) then X{64}(t) = DBGWVR_EL1(m + (UInt(EffectiveMDSELR_EL1_BANK()) * 16)); else X{64}(t) = DBGWVR_EL1(m); end; end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDA == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then Halt(DebugHalt_SoftwareAccess); else if IsFeatureImplemented(FEAT_Debugv8p9) then X{64}(t) = DBGWVR_EL1(m + (UInt(EffectiveMDSELR_EL1_BANK()) * 16)); else X{64}(t) = DBGWVR_EL1(m); end; end; elsif PSTATE.EL == EL3 then if OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then Halt(DebugHalt_SoftwareAccess); else if IsFeatureImplemented(FEAT_Debugv8p9) then X{64}(t) = DBGWVR_EL1(m + (UInt(EffectiveMDSELR_EL1_BANK()) * 16)); else X{64}(t) = DBGWVR_EL1(m); end; end; end; 0-15 MSR DBGWVR<m>_EL1, <Xt> let m:integer = UInt(CRm[3:0]); if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif (!IsFeatureImplemented(FEAT_Debugv8p9) && m >= NUM_WATCHPOINTS) || (IsFeatureImplemented(FEAT_Debugv8p9) && m + (UInt(MDSELR_EL1().BANK) * 16) >= NUM_WATCHPOINTS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDA == '1' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HDFGWTR_EL2().DBGWVRn_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && MDCR_EL2().[TDE,TDA] != '00' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then Halt(DebugHalt_SoftwareAccess); else if IsFeatureImplemented(FEAT_Debugv8p9) then DBGWVR_EL1(m + (UInt(EffectiveMDSELR_EL1_BANK()) * 16)) = X{64}(t); else DBGWVR_EL1(m) = X{64}(t); end; end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && MDCR_EL3().TDA == '1' then Undefined(); elsif HaveEL(EL3) && MDCR_EL3().TDA == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then Halt(DebugHalt_SoftwareAccess); else if IsFeatureImplemented(FEAT_Debugv8p9) then DBGWVR_EL1(m + (UInt(EffectiveMDSELR_EL1_BANK()) * 16)) = X{64}(t); else DBGWVR_EL1(m) = X{64}(t); end; end; elsif PSTATE.EL == EL3 then if OSLSR_EL1().OSLK == '0' && HaltingAllowed() && EDSCR().TDA == '1' then Halt(DebugHalt_SoftwareAccess); else if IsFeatureImplemented(FEAT_Debugv8p9) then DBGWVR_EL1(m + (UInt(EffectiveMDSELR_EL1_BANK()) * 16)) = X{64}(t); else DBGWVR_EL1(m) = X{64}(t); end; end; end; 2026-03-26 20:27:25 2026-03_rel