DC CIPAE
Data or unified Cache line Clean and Invalidate by PA to PoE
when FEAT_MEC is implemented and FEAT_AA64 is implemented
Data or unified Cache line Clean and Invalidate by PA to PoE.
Cache
DC CIPAE is a 64-bit System instruction.
NS
63
63
0
Together with the NSE2 and NSE field, this field specifies the target physical address space.
NSE2NSENSMeaning
0b00b00b0Reserved.
0b00b00b1Reserved.
0b00b10b0Reserved.
0b00b10b1Realm.
0b10b00b0System Agent.
0b10b00b1NS Protected.
0b10b10b0Reserved.
0b10b10b1Reserved.
If {NSE2, NSE, NS} is reserved, then no cache entries are required to be cleaned or invalidated.
When FEAT_RME_GDI is implemented
NS
63
63
0
Together with the NSE field, this field specifies the target physical address space.
NSENSMeaning
0b00b0Reserved.
0b00b1Reserved.
0b10b0Reserved.
0b10b1Realm.
If {NSE, NS} is not {1, 1}, then no cache entries are required to be cleaned or invalidated.
Otherwise
NSE
62
62
62
If FEAT_RME_GDI is implemented, this field together with the NS and NSE2 fields, specifies the target physical address space.
Otherwise, this field and the NS field specify the physical address space
For a description of the values derived by evaluating NS, NSE, and NSE2 together, see DC CIPAE.NS.
NSE2
61
61
0
Together with the NS and NSE field, this field specifies the target physical address space.
For a description of the values derived by evaluating NS and NSE together, see DC CIPAE.NS.
When FEAT_RME_GDI is implemented
61
61
61
Reserved, RES0.
Otherwise
60
56
60:56
Reserved, RES0.
PA[55:52]
55
52
3:0
Extension to PA[51:0] if ID_AA64MMFR0_EL1.PARange = 0111. For more information see PA[51:0].
When FEAT_D128 is implemented
55
52
55:52
Reserved, RES0.
Otherwise
PA
Physical address
51
0
51:0
Physical address to use. No alignment restrictions apply to this PA.
This system instruction is an alias of the SYS instruction.
DC CIPAE, <Xt>
if !(IsFeatureImplemented(FEAT_MEC) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
Undefined();
elsif PSTATE.EL == EL2 then
if !IsCurrentSecurityState(SS_Realm) then
Undefined();
else
AArch64_DC(X{64}(t), CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoE);
end;
elsif PSTATE.EL == EL3 then
AArch64_DC(X{64}(t), CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoE);
end;
2026-03-26 20:27:25
2026-03_rel