DC CIVAC Data or unified Cache line Clean and Invalidate by VA to PoC when FEAT_AA64 is implemented DCCIMVAC Functional AArch32 Clean and Invalidate data cache by address to Point of Coherency. Cache DC CIVAC is a 64-bit System instruction. VA Virtual address to use 63 0 63:0 Virtual address to use. No alignment restrictions apply to this VA. If EL0 access is enabled, when executed at EL0, the instruction may generate a Permission fault, subject to the constraints described in 'MMU faults generated by cache maintenance operations'. Execution of this instruction might require an address translation from VA to PA, and that translation might fault. For more information, see 'The data cache maintenance instruction (DC)'. This system instruction is an alias of the SYS instruction. DC CIVAC, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then if !AArch64_CanTrapDC(CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoC) then ExecuteAsNOP(); elsif !ELIsInHost(EL0) && SCTLR_EL1().UCI == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL0) && HCR_EL2().TPCP == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().DCCIVAC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && SCTLR_EL2().UCI == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else if AArch64_TreatDCAsNOP(CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoC) then ExecuteAsNOP(); else AArch64_DC(X{64}(t), CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoC); end; end; elsif PSTATE.EL == EL1 then if !AArch64_CanTrapDC(CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoC) then ExecuteAsNOP(); elsif EL2Enabled() && HCR_EL2().TPCP == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().DCCIVAC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else if AArch64_TreatDCAsNOP(CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoC) then ExecuteAsNOP(); else AArch64_DC(X{64}(t), CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoC); end; end; elsif PSTATE.EL == EL2 then if !AArch64_CanTrapDC(CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoC) then ExecuteAsNOP(); else if AArch64_TreatDCAsNOP(CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoC) then ExecuteAsNOP(); else AArch64_DC(X{64}(t), CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoC); end; end; elsif PSTATE.EL == EL3 then if AArch64_TreatDCAsNOP(CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoC) then ExecuteAsNOP(); else AArch64_DC(X{64}(t), CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoC); end; end; 2026-03-26 20:27:25 2026-03_rel