DC CIVAPS Clean and Invalidate of Data by VA to PoPS when FEAT_PoPS is implemented and FEAT_AA64 is implemented Clean and Invalidate data in data cache by virtual address to the Point of Physical Storage. This instruction cleans and invalidates all copies of the Location specified in the Xt argument, irrespective of any MECID associated with the Location. Memory accesses resulting from the Clean operation use the MECID associated with the cache entry. Cache DC CIVAPS is a 64-bit System instruction. VA Virtual address to use 63 0 63:0 Virtual address to use. No alignment restrictions apply to this VA. Execution of this instruction might require an address translation from VA to PA, and that translation might fault. For more information, see 'The data cache maintenance instruction (DC)'. This system instruction is an alias of the SYS instruction. DC CIVAPS, <Xt> if !(IsFeatureImplemented(FEAT_PoPS) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TPCP == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGITR2_EL2().nDCCIVAPS == '0') then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_DC(X{64}(t), CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoPS); end; elsif PSTATE.EL == EL2 then AArch64_DC(X{64}(t), CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoPS); elsif PSTATE.EL == EL3 then AArch64_DC(X{64}(t), CacheType_Data, CacheOp_CleanInvalidate, CacheOpScope_PoPS); end; 2026-03-26 20:27:25 2026-03_rel