DC CSW Data or unified Cache line Clean by Set/Way when FEAT_AA64 is implemented DCCSW Functional AArch32 Clean data cache by set/way. Cache DC CSW is a 64-bit System instruction. 63 32 63:32 Reserved, RES0. SetWay 31 4 31:4 Contains two fields: Way, bits[31:32-A], the number of the way to operate on. Set, bits[B-1:L], the number of the set to operate on. Bits[L-1:4] are RES0. A = Log₂(ASSOCIATIVITY), L = Log₂(LINELEN), B = (L + S), S = Log₂(NSETS). ASSOCIATIVITY, LINELEN (line length, in bytes), and NSETS (number of sets) have their usual meanings and are the values for the cache level being operated on. The values of A and S are rounded up to the next integer. Level 3 1 3:1 Cache level to operate on, minus 1. For example, this field is 0 for operations on L1 cache, or 1 for operations on L2 cache. 0 0 0 Reserved, RES0. If this instruction is executed with a set, way or level argument that is larger than the value supported by the implementation then the behavior is CONSTRAINED UNPREDICTABLE and one of the following occurs: The instruction is UNDEFINED. The instruction performs cache maintenance on one of: No cache lines. A single arbitrary cache line. Multiple arbitrary cache lines. This system instruction is an alias of the SYS instruction. DC CSW, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TSW == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().DCCSW == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_DC(X{64}(t), CacheType_Data, CacheOp_Clean, CacheOpScope_SetWay); end; elsif PSTATE.EL == EL2 then AArch64_DC(X{64}(t), CacheType_Data, CacheOp_Clean, CacheOpScope_SetWay); elsif PSTATE.EL == EL3 then AArch64_DC(X{64}(t), CacheType_Data, CacheOp_Clean, CacheOpScope_SetWay); end; 2026-03-26 20:27:25 2026-03_rel