DC ZVA Data Cache Zero by VA when FEAT_AA64 is implemented Zero data cache by address. Zeroes a naturally aligned block of N bytes, where the size of N is identified in DCZID_EL0. This instruction might have the poison-atomic property for IMPLEMENTATION DEFINED regions of physical memory. Cache DC ZVA is a 64-bit System instruction. VA Virtual address to use 63 0 63:0 Virtual address to use. There is no alignment restriction on the address within the block of N bytes that is used. When this instruction is executed, it can generate memory faults or watchpoints which are prioritized in the same way as other memory-related faults or watchpoints. If a synchronous Data Abort fault or a watchpoint is generated, the CM bit in the ESR_ELx.ISS field is set to 0. If the memory region being zeroed is any type of Device memory that does not support unaligned accesses, this instruction generates an Alignment fault which is prioritized in the same way as other Alignment faults that are determined by the memory type. This instruction applies to Normal memory regardless of cacheability attributes. This instruction behaves as a set of Stores to each byte within the block being accessed, and so it: Generates a Permission fault if the translation system does not permit writes to the locations. Requires the same considerations for ordering and the management of coherency as any other store instructions. This system instruction is an alias of the SYS instruction. DC ZVA, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then if !ELIsInHost(EL0) && SCTLR_EL1().DZE == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif EL2Enabled() && !ELIsInHost(EL0) && HCR_EL2().TDZ == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().DCZVA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif ELIsInHost(EL0) && SCTLR_EL2().DZE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_MemZero(X{64}(t), CacheType_Data); end; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2().TDZ == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().DCZVA == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_MemZero(X{64}(t), CacheType_Data); end; elsif PSTATE.EL == EL2 then AArch64_MemZero(X{64}(t), CacheType_Data); elsif PSTATE.EL == EL3 then AArch64_MemZero(X{64}(t), CacheType_Data); end; 2026-03-26 20:27:25 2026-03_rel