DISR_EL1 Deferred Interrupt Status Register when FEAT_RAS is implemented DISR Architectural AArch32 31 0 31 0 31 0 31 0 Records that an SError exception has been consumed by an ESB instruction. RAS DISR_EL1 is a 64-bit register. When DISR_EL1.IDS == '0' 63 32 63:32 Reserved, RES0. A 31 31 31 Set to 1 when an ESB instruction defers an asynchronous SError exception. If the implementation does not include any sources of SError exception that can be synchronized by an Error Synchronization Barrier, then this bit is RES0. AU 30 25 30:25 Reserved, RES0. IDS 24 24 24 Indicates the deferred SError exception type. 0b0 Deferred error uses architecturally-defined format. AU 23 18 23:18 Reserved, RES0. WU 17 16 1:0 Write update. See the description of ESR_ELx.WU for an SError exception. AU When FEAT_RASv2 is implemented 17 16 17:16 Reserved, RES0. Otherwise 15 13 15:13 Reserved, RES0. AET 12 10 12:10 Asynchronous Error Type. See the description of ESR_ELx.AET for an SError exception. AU EA 9 9 9 External abort Type. See the description of ESR_ELx.EA for an SError exception. AU 8 8 8 Reserved, RES0. WnRV 7 7 0 Write-not-Read Valid. See the description of ESR_ELx.WnRV for an SError exception. AU When FEAT_RASv2 is implemented 7 7 7 Reserved, RES0. Otherwise WnR 6 6 0 Write-not-Read. See the description of ESR_ELx.WnR for an SError exception. AU When FEAT_RASv2 is implemented 6 6 6 Reserved, RES0. Otherwise DFSC 5 0 5:0 Fault Status Code. See the description of ESR_ELx.DFSC for an SError exception. AU When DISR_EL1.IDS == '1' 63 32 63:32 Reserved, RES0. A 31 31 31 Set to 1 when an ESB instruction defers an asynchronous SError exception. If the implementation does not include any sources of SError exception that can be synchronized by an Error Synchronization Barrier, then this bit is RES0. AU 30 25 30:25 Reserved, RES0. IDS 24 24 24 Indicates the deferred SError exception type. 0b1 Deferred error uses IMPLEMENTATION DEFINED format. AU ISS 23 0 23:0 IMPLEMENTATION DEFINED syndrome. See the description of ESR_ELx[23:0] for an SError exception. AU When DISR_EL1.IDS == '0' When DISR_EL1.IDS == '1' An indirect write to DISR_EL1 made by an ESB instruction does not require an explicit synchronization operation for the value that is written to be observed by a direct read of DISR_EL1 occurring in program order after the ESB instruction. MRS <Xt>, DISR_EL1 if !IsFeatureImplemented(FEAT_RAS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && (HCR_EL2().AMO == '1' || (IsFeatureImplemented(FEAT_DoubleFault2) && IsHCRXEL2Enabled() && HCRX_EL2().TMEA == '1')) then X{64}(t) = VDISR_EL2(); elsif HaveEL(EL3) && EffectiveSCR_EL3_EnDSE() == '1' then X{64}(t) = VDISR_EL3(); elsif HaveEL(EL3) && !Halted() && SCR_EL3().EA == '1' then X{64}(t) = Zeros{64}; else X{64}(t) = DISR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EffectiveSCR_EL3_EnDSE() == '1' then X{64}(t) = VDISR_EL3(); elsif HaveEL(EL3) && !Halted() && SCR_EL3().EA == '1' then X{64}(t) = Zeros{64}; else X{64}(t) = DISR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = DISR_EL1(); end; MSR DISR_EL1, <Xt> if !IsFeatureImplemented(FEAT_RAS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EL2Enabled() && (HCR_EL2().AMO == '1' || (IsFeatureImplemented(FEAT_DoubleFault2) && IsHCRXEL2Enabled() && HCRX_EL2().TMEA == '1')) then VDISR_EL2() = X{64}(t); elsif HaveEL(EL3) && EffectiveSCR_EL3_EnDSE() == '1' then VDISR_EL3() = X{64}(t); elsif HaveEL(EL3) && !Halted() && SCR_EL3().EA == '1' then return; else DISR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EffectiveSCR_EL3_EnDSE() == '1' then VDISR_EL3() = X{64}(t); elsif HaveEL(EL3) && !Halted() && SCR_EL3().EA == '1' then return; else DISR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then DISR_EL1() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel