DSPSR_EL0 Debug Saved Program Status Register when FEAT_AA64 is implemented DSPSR Architectural AArch32 31 0 31 0 31 0 31 0 DSPSR2 Architectural AArch32 63 32 31 0 63 32 31 0 when FEAT_Debugv8p9 is implemented Holds the saved process state for Debug state. On entering Debug state, PSTATE information is written to this register. On exiting Debug state, values are copied from this register to PSTATE. Debug Secondary DSPSR_EL0 is a 64-bit register. When FEAT_AA32 is implemented and exiting Debug state to AArch32 state exiting Debug state to AArch32 state 63 37 63:37 Reserved, RES0. UINJ 36 36 0 Inject Undefined Instruction exception. Copied to PSTATE.UINJ on exiting Debug state. AU When FEAT_UINJ is implemented 36 36 36 Reserved, RES0. Otherwise 35 32 35:32 Reserved, RES0. N 31 31 31 Negative Condition flag. Copied to PSTATE.N on exiting Debug state. AU Z 30 30 30 Zero Condition flag. Copied to PSTATE.Z on exiting Debug state. AU C 29 29 29 Carry Condition flag. Copied to PSTATE.C on exiting Debug state. AU V 28 28 28 Overflow Condition flag. Copied to PSTATE.V on exiting Debug state. AU Q 27 27 27 Overflow or saturation flag. Copied to PSTATE.Q on exiting Debug state. AU IT 26 25 15:10, 26:25 If-Then. Copied to PSTATE.IT on exiting Debug state. On exiting Debug state, DSPSR_EL0.IT must contain a value that is valid for the instruction being returned to. The IT field is split as follows: IT[1:0] is DSPSR_EL0[26:25]. IT[7:2] is DSPSR_EL0[15:10]. 15 10 26 25 AU DIT 24 24 0 Data Independent Timing. Copied to PSTATE.DIT on exiting Debug state. AU When FEAT_DIT is implemented 24 24 24 Reserved, RES0. Otherwise SSBS 23 23 0 Speculative Store Bypass. Copied to PSTATE.SSBS on exiting Debug state. AU When FEAT_SSBS is implemented 23 23 23 Reserved, RES0. Otherwise PAN 22 22 0 Privileged Access Never. Copied to PSTATE.PAN on exiting Debug state. AU When FEAT_PAN is implemented 22 22 22 Reserved, RES0. Otherwise SS 21 21 21 Software Step. Copied to PSTATE.SS on exiting Debug state. AU IL 20 20 20 Illegal Execution state. Copied to PSTATE.IL on exiting Debug state. AU GE 19 16 19:16 Greater than or Equal flags. Copied to PSTATE.GE on exiting Debug state. AU IT[7:2] 15 10 15:10, 26:25 This field is bits[7:2] of IT[7:0]. See IT[1:0] for the field description. E 9 9 9 Endianness. Copied to PSTATE.E on exiting Debug state. If the implementation does not support big-endian operation, DSPSR_EL0.E is RES0. If the implementation does not support little-endian operation, DSPSR_EL0.E is RES1. On exiting Debug state, if the implementation does not support big-endian operation at the Exception level being returned to, DSPSR_EL0.E is RES0, and if the implementation does not support little-endian operation at the Exception level being returned to, DSPSR_EL0.E is RES1. AU A 8 8 8 SError exception mask. Copied to PSTATE.A on exiting Debug state. AU I 7 7 7 IRQ interrupt mask. Copied to PSTATE.I on exiting Debug state. AU F 6 6 6 FIQ interrupt mask. Copied to PSTATE.F on exiting Debug state. AU T 5 5 5 T32 Instruction set state. Copied to PSTATE.T on exiting Debug state. AU M[4] 4 4 4 Execution state. Copied to PSTATE.nRW on exiting Debug state. 0b1 AArch32 execution state. AU M[3:0] 3 0 3:0 AArch32 Mode. Copied to PSTATE.M[3:0] on exiting Debug state. Other values are reserved. If DSPSR_EL0.M[3:0] has a Reserved value, or a value for an unimplemented Exception level, exiting Debug state is an illegal return event, as described in 'Illegal return events from AArch64 state'. 0b0000 User. 0b0001 FIQ. 0b0010 IRQ. 0b0011 Supervisor. 0b0110 Monitor. When FEAT_EL3 is implemented 0b0111 Abort. 0b1010 Hyp. 0b1011 Undefined. 0b1111 System. AU When FEAT_AA64 is implemented and entering or exiting Debug state from or to AArch64 state entering or exiting Debug state from or to AArch64 state 63 37 63:37 Reserved, RES0. UINJ 36 36 0 Inject Undefined Instruction exception. Set to the value of PSTATE.UINJ on entering Debug state, and copied to PSTATE.UINJ on exiting Debug state. AU When FEAT_UINJ is implemented 36 36 36 Reserved, RES0. Otherwise PACM 35 35 0 PACM. Set to the value of PSTATE.PACM on entering Debug state, and copied to PSTATE.PACM on exiting Debug state. AU When FEAT_PAuth_LR is implemented 35 35 35 Reserved, RES0. Otherwise EXLOCK 34 34 0 Exception return state lock. Set to the value of PSTATE.EXLOCK on entering Debug state, and copied to PSTATE.EXLOCK on exiting Debug state. AU When FEAT_GCS is implemented 34 34 34 Reserved, RES0. Otherwise 33 33 33 Reserved, RES0. PM 32 32 0 Profiling exception mask bit. Set to the value of PSTATE.PM on entering Debug state, and copied to PSTATE.PM on exiting Debug state. AU When FEAT_EBEP is implemented 32 32 32 Reserved, RES0. Otherwise N 31 31 31 Negative Condition flag. Set to the value of PSTATE.N on entering Debug state, and copied to PSTATE.N on exiting Debug state. AU Z 30 30 30 Zero Condition flag. Set to the value of PSTATE.Z on entering Debug state, and copied to PSTATE.Z on exiting Debug state. AU C 29 29 29 Carry Condition flag. Set to the value of PSTATE.C on entering Debug state, and copied to PSTATE.C on exiting Debug state. AU V 28 28 28 Overflow Condition flag. Set to the value of PSTATE.V on entering Debug state, and copied to PSTATE.V on exiting Debug state. AU 27 26 27:26 Reserved, RES0. TCO 25 25 0 Tag Check Override. Set to the value of PSTATE.TCO on entering Debug state, and copied to PSTATE.TCO on exiting Debug state. AU When FEAT_MTE is implemented 25 25 25 Reserved, RES0. Otherwise DIT 24 24 0 Data Independent Timing. Set to the value of PSTATE.DIT on entering Debug state, and copied to PSTATE.DIT on exiting Debug state. AU When FEAT_DIT is implemented 24 24 24 Reserved, RES0. Otherwise UAO 23 23 0 User Access Override. Set to the value of PSTATE.UAO on entering Debug state, and copied to PSTATE.UAO on exiting Debug state. AU When FEAT_UAO is implemented 23 23 23 Reserved, RES0. Otherwise PAN 22 22 0 Privileged Access Never. Set to the value of PSTATE.PAN on entering Debug state, and copied to PSTATE.PAN on exiting Debug state. AU When FEAT_PAN is implemented 22 22 22 Reserved, RES0. Otherwise SS 21 21 21 Software Step. Set to the value of PSTATE.SS on entering Debug state, and conditionally copied to PSTATE.SS on exiting Debug state. AU IL 20 20 20 Illegal Execution state. Set to the value of PSTATE.IL on entering Debug state, and copied to PSTATE.IL on exiting Debug state. AU 19 14 19:14 Reserved, RES0. ALLINT 13 13 0 All IRQ or FIQ interrupts mask. Set to the value of PSTATE.ALLINT on entering Debug state, and copied to PSTATE.ALLINT on exiting Debug state. AU When FEAT_NMI is implemented 13 13 13 Reserved, RES0. Otherwise SSBS 12 12 0 Speculative Store Bypass. Set to the value of PSTATE.SSBS on entering Debug state, and copied to PSTATE.SSBS on exiting Debug state. AU When FEAT_SSBS is implemented 12 12 12 Reserved, RES0. Otherwise BTYPE 11 10 1:0 Branch Type Indicator. Set to the value of PSTATE.BTYPE on entering Debug state, and copied to PSTATE.BTYPE on exiting Debug state. AU When FEAT_BTI is implemented 11 10 11:10 Reserved, RES0. Otherwise D 9 9 9 Debug exception mask. Set to the value of PSTATE.D on entering Debug state, and copied to PSTATE.D on exiting Debug state. AU A 8 8 8 SError exception mask. Set to the value of PSTATE.A on entering Debug state, and copied to PSTATE.A on exiting Debug state. AU I 7 7 7 IRQ interrupt mask. Set to the value of PSTATE.I on entering Debug state, and copied to PSTATE.I on exiting Debug state. AU F 6 6 6 FIQ interrupt mask. Set to the value of PSTATE.F on entering Debug state, and copied to PSTATE.F on exiting Debug state. AU 5 5 5 Reserved, RES0. M[4] 4 4 4 Execution state. Set to 0, the value of PSTATE.nRW, on entering Debug state from AArch64 state, and copied to PSTATE.nRW on exiting Debug state. 0b0 AArch64 execution state. AU M[3:0] 3 0 3:0 AArch64 Exception level and selected Stack Pointer. Other values are reserved. If DSPSR_EL0.M[3:0] has a Reserved value, or a value for an unimplemented Exception level, exiting Debug state is an illegal return event, as described in 'Illegal return events from AArch64 state'. The bits in this field are interpreted as follows: M[3:2] is set to the value of PSTATE.EL on entering Debug state and copied to PSTATE.EL on exiting Debug state. M[1] is unused and is 0 for all non-reserved values. M[0] is set to the value of PSTATE.SP on entering Debug state and copied to PSTATE.SP on exiting Debug state. 0b0000 EL0. 0b0100 EL1 with SP_EL0 (EL1t). 0b0101 EL1 with SP_EL1 (EL1h). 0b1000 EL2 with SP_EL0 (EL2t). 0b1001 EL2 with SP_EL2 (EL2h). 0b1100 EL3 with SP_EL0 (EL3t). When FEAT_EL3 is implemented 0b1101 EL3 with SP_EL3 (EL3h). When FEAT_EL3 is implemented AU When FEAT_AA32 is implemented and exiting Debug state to AArch32 state When FEAT_AA64 is implemented and entering or exiting Debug state from or to AArch64 state MRS <Xt>, DSPSR_EL0 if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif !Halted() then Undefined(); else X{64}(t) = DSPSR_EL0(); end; MSR DSPSR_EL0, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif !Halted() then Undefined(); else DSPSR_EL0() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel