ERXGSR_EL1 Selected Error Record Group Status Register when FEAT_RASv2 is implemented Shows the status for the records in a group of error records. Accesses ERRGSR for the group of error records <n> selected by ERRSELR_EL1.SEL[15:6]. RAS ERXGSR_EL1 is a 64-bit register. S<q> 63 0 63:0 The status for error record <m>, where m = q + (UInt(ERRSELR_EL1.SEL[15:6])×64). A read-only copy of ERR<m>STATUS.V. 63 0 0b0 No error. 0b1 One or more errors. When !(error record m is implemented and error record m supports this type of reporting) RES0 If ERRIDR_EL1.NUM is 0x0000 or ERRSELR_EL1.SEL is greater than or equal to ERRIDR_EL1.NUM, then one of the following occurs: An UNKNOWN group of error records are selected. ERXGSR_EL1 is RAZ. Direct reads of ERXGSR_EL1 are NOPs. Direct reads of ERXGSR_EL1 are UNDEFINED. MRS <Xt>, ERXGSR_EL1 if !IsFeatureImplemented(FEAT_RASv2) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TERR == '1' then Undefined(); elsif EL2Enabled() && HCR_EL2().TERR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT2) && ((HaveEL(EL3) && SCR_EL3().FGTEn2 == '0') || HFGRTR2_EL2().nERXGSR_EL1 == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().TERR == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ERRGSR(UInt(ERRSELR_EL1().SEL[15:6])); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().TERR == '1' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().TERR == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ERRGSR(UInt(ERRSELR_EL1().SEL[15:6])); end; elsif PSTATE.EL == EL3 then X{64}(t) = ERRGSR(UInt(ERRSELR_EL1().SEL[15:6])); end; 2026-03-26 20:27:25 2026-03_rel