<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="True" is_internal="True" is_stub_entry="False">
      <reg_short_name>ERXPFGF_EL1</reg_short_name>
        
        <reg_long_name>Selected Pseudo-fault Generation Feature Register</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_RASv1p1 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Accesses <register_link state="ext" id="ext-errnpfgf.xml">ERR&lt;n&gt;PFGF</register_link> for the error record &lt;n&gt; selected by <register_link state="AArch64" id="AArch64-errselr_el1.xml">ERRSELR_EL1</register_link>.SEL.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
          <reg_group>RAS</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>ERXPFGF_EL1 is a 64-bit register.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        






<fields id="fieldset_0" length="64">
  <text_before_fields/>
  <field id="fieldset_0-63_0" has_partial_fieldset="False" is_linked_to_partial_fieldset="False" is_access_restriction_possible="False" is_variable_length="False" is_constant_value="False" is_partial_field="False" is_conditional_field_name="False">
    <field_name>ERRnPFGF</field_name>
    <field_msb>63</field_msb>
    <field_lsb>0</field_lsb>
    <rel_range>63:0</rel_range>
    <field_description order="before">
      <para>ERXPFGF_EL1 accesses <register_link state="ext" id="ext-errnpfgf.xml">ERR&lt;n&gt;PFGF</register_link>, where &lt;n&gt; is the value in <register_link state="AArch64" id="AArch64-errselr_el1.xml">ERRSELR_EL1</register_link>.SEL.</para>
    </field_description>
  </field>
  <text_after_fields/>
</fields>




<reg_fieldset length="64">
  <fieldat id="fieldset_0-63_0" msb="63" lsb="0"/>
</reg_fieldset>


      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>If <register_link state="AArch64" id="AArch64-erridr_el1.xml">ERRIDR_EL1</register_link>.NUM is <hexnumber>0x0000</hexnumber> or <register_link state="AArch64" id="AArch64-errselr_el1.xml">ERRSELR_EL1</register_link>.SEL is greater than or equal to <register_link state="AArch64" id="AArch64-erridr_el1.xml">ERRIDR_EL1</register_link>.NUM, then one of the following occurs:</para>

      </access_permission_text>
      <access_permission_text>
        <list type="unordered">
<listitem><content>An <arm-defined-word>UNKNOWN</arm-defined-word> error record is selected.</content>
</listitem><listitem><content>ERXPFGF_EL1 is RAZ.</content>
</listitem><listitem><content>Direct reads of ERXPFGF_EL1 are NOPs.</content>
</listitem><listitem><content>Direct reads of ERXPFGF_EL1 are <arm-defined-word>UNDEFINED</arm-defined-word>.</content>
</listitem></list>

      </access_permission_text>
      <access_permission_text>
        <para>If <register_link state="AArch64" id="AArch64-errselr_el1.xml">ERRSELR_EL1</register_link>.SEL selects an error record owned by a node that does not implement the Common Fault Injection Model Extension, then one of the following occurs:</para>

      </access_permission_text>
      <access_permission_text>
        <list type="unordered">
<listitem><content>ERXPFGF_EL1 is RAZ.</content>
</listitem><listitem><content>Direct reads of ERXPFGF_EL1 are NOPs.</content>
</listitem><listitem><content>Direct reads of ERXPFGF_EL1 are <arm-defined-word>UNDEFINED</arm-defined-word>.</content>
</listitem></list>

      </access_permission_text>
      <access_permission_text>
        <note><para>A node does not implement the Common Fault Injection Model Extension if <register_link id="ext-errnfr.xml" state="ext">ERR&lt;q&gt;FR</register_link>.INJ reads as <binarynumber>0b00</binarynumber>. &lt;q&gt; is the index of the first error record owned by the same node as error record &lt;n&gt;, where &lt;n&gt; is the value in <register_link state="AArch64" id="AArch64-errselr_el1.xml">ERRSELR_EL1</register_link>.SEL. If the node owns a single record then q = n.</para></note>
      </access_permission_text>
      <access_permission_text>
        <para>If <register_link state="AArch64" id="AArch64-errselr_el1.xml">ERRSELR_EL1</register_link>.SEL is not the index of the first error record owned by a node, then <register_link state="ext" id="ext-errnpfgf.xml">ERR&lt;n&gt;PFGF</register_link> is not present, meaning reads of ERXPFGF_EL1 are <arm-defined-word>RES0</arm-defined-word>.</para>

      </access_permission_text>
      <access_permission_text>
        <para><register_link state="ext" id="ext-errnpfgf.xml">ERR&lt;n&gt;PFGF</register_link> describes additional constraints that also apply when <register_link state="ext" id="ext-errnpfgf.xml">ERR&lt;n&gt;PFGF</register_link> is accessed through ERXPFGF_EL1.</para>
      </access_permission_text>





    
        
        <access_mechanism accessor="MRS ERXPFGF_EL1" type="SystemAccessor">
            <encoding>
            <access_instruction>MRS &lt;Xt&gt;, ERXPFGF_EL1</access_instruction>
                
                <enc n="op0" v="0b11"/>
                
                <enc n="op1" v="0b000"/>
                
                <enc n="CRn" v="0b0101"/>
                
                <enc n="CRm" v="0b0100"/>
                
                <enc n="op2" v="0b100"/>
            </encoding>
            <access_permission>
                <ps name="MRS" sections="1" secttype="access_permission">
                <pstext>
if !IsFeatureImplemented(FEAT_RASv1p1) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SCR_EL3().FIEN == '0' then
        Undefined();
    elsif EL2Enabled() &amp;&amp; HCR_EL2().FIEN == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') &amp;&amp; HFGRTR_EL2().ERXPFGF_EL1 == '1' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif HaveEL(EL3) &amp;&amp; SCR_EL3().FIEN == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = ERRPFGF(UInt(ERRSELR_EL1().SEL));
    end;
elsif PSTATE.EL == EL2 then
    if HaveEL(EL3) &amp;&amp; EL3SDDUndefPriority() &amp;&amp; SCR_EL3().FIEN == '0' then
        Undefined();
    elsif HaveEL(EL3) &amp;&amp; SCR_EL3().FIEN == '0' then
        if EL3SDDUndef() then
            Undefined();
        else
            AArch64_SystemAccessTrap(EL3, 0x18);
        end;
    else
        X{64}(t) = ERRPFGF(UInt(ERRSELR_EL1().SEL));
    end;
elsif PSTATE.EL == EL3 then
    X{64}(t) = ERRPFGF(UInt(ERRSELR_EL1().SEL));
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>