FPCR Floating-point Control Register when FEAT_AA64 is implemented FPSCR Architectural AArch32 26 15 26 15 26 15 26 15 FPSCR Architectural AArch32 12 8 12 8 12 8 12 8 Controls behavior of the floating-point instructions. Float It is IMPLEMENTATION DEFINED whether the Len and Stride fields can be programmed to nonzero values, which will cause some AArch32 floating-point instruction encodings to be UNDEFINED, or whether these fields are RAZ. FPCR is a 64-bit register. 63 27 63:27 Reserved, RES0. AHP 26 26 26 Alternative half-precision control bit. This bit is used only for conversions between half-precision floating-point and other floating-point formats. The data-processing instructions added as part of the FEAT_FP16 extension always use the IEEE half-precision format, and ignore the value of this bit. 0b0 IEEE half-precision format selected. 0b1 Alternative half-precision format selected. AU DN 25 25 25 Default NaN use for NaN propagation. 0b0 NaN operands propagate through to the output of a floating-point operation. 0b1 Any operation involving one or more NaNs returns the Default NaN. This bit has no effect on the output of the FABS and FNEG instructions. This bit has no effect on the output of the FMAX, FMAXP, FMAXV, FMIN, FMINP, and FMINV instructions when FPCR.AH is 1. AU FZ 24 24 24 Flushing denormalized numbers to zero control bit. For more information, see 'Flushing denormalized numbers to zero' and the pseudocode of the floating-point instructions. 0b0 If FPCR.AH is 0, the flushing to zero of single-precision and double-precision denormalized inputs to, and outputs of, floating-point instructions not enabled by this control, but other factors might cause the input denormalized numbers to be flushed to zero. If FPCR.AH is 1, the flushing to zero of single-precision and double-precision denormalized outputs of floating-point instructions not enabled by this control, but other factors might cause the input denormalized numbers to be flushed to zero. 0b1 If FPCR.AH is 0, denormalized single-precision and double-precision inputs to, and outputs from, floating-point instructions are flushed to zero. If FPCR.AH is 1, denormalized single-precision and double-precision outputs from floating-point instructions are flushed to zero. AU RMode 23 22 23:22 Rounding Mode control field. The following instructions ignore this field and use Round to Nearest mode: All FP8 instructions, as described in 'Summary of FP8 instruction behaviors'. When FPCR.AH is 1, then the floating-point reciprocal estimate, step and exponent instructions, floating-point square root estimate and step instructions, and instructions that follow Alternate BFloat16 behaviors, as defined in 'Rounding'. 0b00 Round to Nearest (RN) mode. 0b01 Round towards Plus Infinity (RP) mode. 0b10 Round towards Minus Infinity (RM) mode. 0b11 Round towards Zero (RZ) mode. AU Stride 21 20 21:20 This field has no function in AArch64 state, and nonzero values are ignored during execution in AArch64 state. This field is included only for context saving and restoration of the AArch32 FPSCR.Stride field. AU When an implementation implements FPSCR.{Stride,Len} as RAZ RAZ/WI FZ16 19 19 0 Flushing denormalized numbers to zero control bit on half-precision data-processing instructions. For more information, see 'Flushing denormalized numbers to zero' and the pseudocode of the floating-point instructions. 0b0 For some instructions, this bit disables flushing to zero of inputs and outputs that are half-precision denormalized numbers. 0b1 Flushing denormalized numbers to zero enabled. For some instructions that do not convert a half-precision input to a higher precision output, this bit enables flushing to zero of inputs and outputs that are half-precision denormalized numbers. AU When FEAT_FP16 is implemented 19 19 19 Reserved, RES0. Otherwise Len 18 16 18:16 This field has no function in AArch64 state, and nonzero values are ignored during execution in AArch64 state. This field is included only for context saving and restoration of the AArch32 FPSCR.Len field. AU When an implementation implements FPSCR.{Stride,Len} as RAZ RAZ/WI IDE 15 15 15 Input Denormal floating-point exception trap enable. When the PE is in Streaming SVE mode, and FEAT_SME_FA64 is not implemented or not enabled, the value of FPCR.IDE is treated as 0 for all purposes other than a direct read or write of the FPCR. The Effective value of this bit controls both scalar and vector floating-point arithmetic. 0b0 Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.IDC bit is set to 1. 0b1 Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IDC bit. AU When an implementation does not implement trapping of Input Denormal floating-point exceptions RAZ/WI 14 14 14 Reserved, RES0. EBF 13 13 0 The value of this bit controls the numeric behaviors of BFloat16 dot product calculations performed by the BFDOT, BFMMLA, BFMOPA, and BFMOPS instructions. If FEAT_SME2 is implemented, this also controls BFVDOT instruction. When ID_AA64ISAR1_EL1.BF16 and ID_AA64ZFR0_EL1.BF16 are 0b0010, the PE supports the FPCR.EBF field. Otherwise, FPCR.EBF is RES0. 0b0 These instructions use the standard BFloat16 behaviors: Ignoring the FPCR.RMode control and using the rounding mode defined for BFloat16. For more information, see 'Round to Odd mode'. Flushing denormalized inputs and outputs to zero, as if the FPCR.FZ and FPCR.FIZ controls had the value '1'. Performing unfused multiplies and additions with intermediate rounding of all products and sums. 0b1 These instructions use the extended BFloat16 behaviors: Supporting all four IEEE 754 rounding modes selected by the FPCR.RMode control. Optionally, flushing denormalized inputs and outputs to zero, as governed by the FPCR.FZ and FPCR.FIZ controls. Performing a fused two-way sum-of-products for each pair of adjacent BFloat16 elements, without intermediate rounding of the products, but rounding the single-precision sum before addition to the accumulator. Generating the default NaN as intermediate sum-of-products when any multiplier input is a NaN, or any product is infinity × 0.0, or there are infinite products with differing signs. Generating an intermediate sum-of-products of the same infinity when there are infinite products all with the same sign. AU When FEAT_EBF16 is implemented 13 13 13 Reserved, RES0. Otherwise IXE 12 12 12 Inexact floating-point exception trap enable. When the PE is in Streaming SVE mode, and FEAT_SME_FA64 is not implemented or not enabled, the value of FPCR.IXE is treated as 0 for all purposes other than a direct read or write of the FPCR. The Effective value of this bit controls both scalar and vector floating-point arithmetic. 0b0 Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.IXC bit is set to 1. 0b1 Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IXC bit. AU When an implementation does not implement trapping of Inexact floating-point exceptions RAZ/WI UFE 11 11 11 Underflow floating-point exception trap enable. When the PE is in Streaming SVE mode, and FEAT_SME_FA64 is not implemented or not enabled, the value of FPCR.UFE is treated as 0 for all purposes other than a direct read or write of the FPCR. The Effective value of this bit controls both scalar and vector floating-point arithmetic. 0b0 Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.UFC bit is set to 1. 0b1 Trapped exception handling selected. If the floating-point exception occurs and Flush-to-zero is not enabled, the PE does not update the FPSR.UFC bit. AU When an implementation does not implement trapping of Underflow floating-point exceptions RAZ/WI OFE 10 10 10 Overflow floating-point exception trap enable. When the PE is in Streaming SVE mode, and FEAT_SME_FA64 is not implemented or not enabled, the value of FPCR.OFE is treated as 0 for all purposes other than a direct read or write of the FPCR. The Effective value of this bit controls both scalar and vector floating-point arithmetic. 0b0 Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.OFC bit is set to 1. 0b1 Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.OFC bit. AU When an implementation does not implement trapping of Overflow floating-point exceptions RAZ/WI DZE 9 9 9 Divide by Zero floating-point exception trap enable. When the PE is in Streaming SVE mode, and FEAT_SME_FA64 is not implemented or not enabled, the value of FPCR.DZE is treated as 0 for all purposes other than a direct read or write of the FPCR. The Effective value of this bit controls both scalar and vector floating-point arithmetic. 0b0 Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.DZC bit is set to 1. 0b1 Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.DZC bit. AU When an implementation does not implement trapping of Divide by Zero floating-point exceptions RAZ/WI IOE 8 8 8 Invalid Operation floating-point exception trap enable. When the PE is in Streaming SVE mode, and FEAT_SME_FA64 is not implemented or not enabled, the value of FPCR.IOE is treated as 0 for all purposes other than a direct read or write of the FPCR. The Effective value of this bit controls both scalar and vector floating-point arithmetic. 0b0 Untrapped exception handling selected. If the floating-point exception occurs, the FPSR.IOC bit is set to 1. 0b1 Trapped exception handling selected. If the floating-point exception occurs, the PE does not update the FPSR.IOC bit. AU When an implementation does not implement trapping of Invalid Operation floating-point exceptions RAZ/WI 7 3 7:3 Reserved, RES0. NEP 2 2 0 Controls how the output elements other than the lowest element of the vector are determined for Advanced SIMD scalar instructions. When the PE is in Streaming SVE mode, and FEAT_SME_FA64 is not implemented or not enabled, the value of FPCR.NEP is treated as 0 for all purposes other than a direct read or write of the FPCR. 0b0 Does not affect how the output elements other than the lowest are determined for Advanced SIMD scalar instructions. 0b1 The output elements other than the lowest are taken from the following registers: For 3-input scalar versions of the FMLA (by element) and FMLS (by element) instructions, the <Hd>, <Sd>, or <Dd> register. For 3-input versions of the FMADD, FMSUB, FNMADD, and FNMSUB instructions, the <Ha>, <Sa>, or <Da> register. For 2-input scalar versions of the FACGE, FACGT, FCMEQ (register), FCMGE (register), and FCMGT (register) instructions, the <Hm>, <Sm>, or <Dm> register. For 2-input scalar versions of the FABD, FADD (scalar), FDIV (scalar), FMAX (scalar), FMAXNM (scalar), FMIN (scalar), FMINNM (scalar), FMUL (by element), FMUL (scalar), FMULX (by element), FMULX, FNMUL (scalar), FRECPS, FRSQRTS, and FSUB (scalar) instructions, the <Hn>, <Sn>, or <Dn> register. For 1-input scalar versions of the following instructions, the <Hd>, <Sd>, or <Dd> register: The (vector) versions of the FCVTAS, FCVTAU, FCVTMS, FCVTMU, FCVTNS, FCVTNU, FCVTPS, and FCVTPU instructions. The (vector, fixed-point) and (vector, integer) versions of the FCVTZS, FCVTZU, SCVTF, and UCVTF instructions. The (scalar) versions of the FABS, FNEG, FRINT32X, FRINT32Z, FRINT64X, FRINT64Z, FRINTA, FRINTI, FRINTM, FRINTN, FRINTP, FRINTX, FRINTZ, and FSQRT instructions. The (scalar, fixed-point) and (scalar, integer) versions of the SCVTF and UCVTF instructions. The BFCVT, FCVT, FCVTXN, FRECPE, FRECPX, and FRSQRTE instructions. AU When FEAT_AFP is implemented 2 2 2 Reserved, RES0. Otherwise AH 1 1 0 Alternate Handling. Controls alternate handling of floating-point numbers. The Arm architecture supports two models for handling some of the corner cases of the floating-point behaviors, such as the nature of flushing of denormalized numbers, the detection of tininess and other exceptions and a range of other behaviors. The value of the FPCR.AH bit selects between these models. For more information on the FPCR.AH bit, see 'Flushing denormalized numbers to zero', 'Floating-point exceptions and exception traps' and the pseudocode of the floating-point instructions. AU When FEAT_AFP is implemented 1 1 1 Reserved, RES0. Otherwise FIZ 0 0 0 Flush Inputs to Zero. Controls whether single-precision, double-precision and BFloat16 input operands that are denormalized numbers are flushed to zero. For more information, see 'Flushing denormalized numbers to zero' and the pseudocode of the floating-point instructions. 0b0 The flushing to zero of single-precision and double-precision denormalized inputs to floating-point instructions not enabled by this control, but other factors might cause the input denormalized numbers to be flushed to zero. 0b1 Denormalized single-precision and double-precision inputs to most floating-point instructions flushed to zero. AU When FEAT_AFP is implemented 0 0 0 Reserved, RES0. Otherwise MRS <Xt>, FPCR if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif !ELIsInHost(EL0) && CPACR_EL1().FPEN != '11' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x00); else AArch64_SystemAccessTrap(EL1, 0x07); end; elsif ELIsInHost(EL0) && CPTR_EL2().FPEN != '11' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else X{64}(t) = FPCR(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif CPACR_EL1().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else X{64}(t) = FPCR(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else X{64}(t) = FPCR(); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TFP == '1' then AArch64_SystemAccessTrap(EL3, 0x07); else X{64}(t) = FPCR(); end; end; MSR FPCR, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif !ELIsInHost(EL0) && CPACR_EL1().FPEN != '11' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x00); else AArch64_SystemAccessTrap(EL1, 0x07); end; elsif ELIsInHost(EL0) && CPTR_EL2().FPEN != '11' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else FPCR() = X{64}(t); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif CPACR_EL1().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else FPCR() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else FPCR() = X{64}(t); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TFP == '1' then AArch64_SystemAccessTrap(EL3, 0x07); else FPCR() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel