FPEXC32_EL2 Floating-Point Exception Control Register when FEAT_AA32EL1 is implemented and FEAT_AA64 is implemented FPEXC Architectural AArch32 31 0 31 0 31 0 31 0 Allows access to the AArch32 register FPEXC from AArch64 state only. Its value has no effect on execution in AArch64 state. Float If EL2 is not implemented but EL3 is implemented, and EL1 is capable of using AArch32, then this register is not RES0. Implemented only if the implementation includes the Advanced SIMD and floating-point functionality. FPEXC32_EL2 is a 64-bit register. 63 32 63:32 Reserved, RES0. EX 31 31 31 Exception bit. AU RAZ/WI EN 30 30 30 Enables access to the Advanced SIMD and floating-point functionality from all Exception levels, except that setting this field to 0 does not disable the following: VMSR accesses to the FPEXC or FPSID. VMRS accesses from the FPEXC, FPSID, MVFR0, MVFR1, or MVFR2. Execution of Advanced SIMD and floating-point instructions in AArch32 state can be disabled or trapped by the following controls: CPACR.cp10, or, if executing at EL0, CPACR_EL1.FPEN. FPEXC.EN. If executing in Non-secure state: HCPTR.TCP10, or if EL2 is using AArch64, CPTR_EL2.TFP. NSACR.cp10, or if EL3 is using AArch64, CPTR_EL3.TFP. For Advanced SIMD instructions only: CPACR.ASEDIS. If executing in Non-secure state, HCPTR.TASE and NSACR.NSASEDIS. See the descriptions of the controls for more information. When executing at EL0 using AArch32:If EL1 is using AArch64, then the Effective value of FPEXC.EN is 1.If EL2 is using AArch64 and is enabled in the current Security state, HCR_EL2.TGE is 1, and the Effective value of HCR_EL2.RW is 1, then the Effective value of FPEXC.EN is 1. However, Arm deprecates using the value of FPEXC32_EL2.EN to determine behavior. 0b0 Accesses to the FPSCR, and any of the SIMD and floating-point registers Q0-Q15, including their views as D0-D31 registers or S0-S31 registers, are UNDEFINED at all Exception levels. 0b1 This control permits access to the Advanced SIMD and floating-point functionality at all Exception levels. AU DEX 29 29 29 Defined synchronous exception on floating-point execution. This field identifies whether a synchronous exception generated by the attempted execution of an instruction was generated by an unallocated encoding. The instruction must be in the encoding space that is identified by the pseudocode function ExecutingCP10or11Instr() returning TRUE. This field also indicates whether the FPEXC32_EL2.TFV field is valid. The meaning of this bit is: On an exception that sets this bit to 1 the exception-handling routine must clear this bit to 0. On an implementation that both does not support trapping of floating-point exceptions and implements the AArch32 FPSCR.{Stride, Len} fields as RAZ, this bit is RES0. 0b0 The exception was generated by the attempted execution of an unallocated instruction in the encoding space that is identified by the pseudocode function ExecutingCP10or11Instr(). If FPEXC32_EL2.TFV is RW then it is invalid and UNKNOWN. If FPEXC32_EL2.{IDF, IXF, UFF, OFF, DZF, IOF} are RW then they are invalid and UNKNOWN. 0b1 The exception was generated during the execution of an allocated encoding. FPEXC32_EL2.TFV is valid and indicates the cause of the exception. AU FP2V 28 28 28 FPINST2 instruction Valid bit. From Armv8.0, this bit is RES0. AU RES0 VV 27 27 27 VECITR valid bit. From Armv8, this bit is RES0. AU RES0 TFV 26 26 26 Trapped Fault Valid bit. Valid only when the value of FPEXC32_EL2.DEX is 1. When valid, it indicates the cause of the exception and therefore whether FPEXC32_EL2.{IDF, IXF, UFF, OFF, DZF, IOF} are valid. This bit returns a status value and ignores writes. When the value of FPEXC32_EL2.DEX is 0 and this bit is RW, this bit is invalid and UNKNOWN. 0b0 The exception was caused by the execution of a floating-point VABS, VADD, VDIV, VFMA, VFMS, VFNMA, VFNMS, VMLA, VMLS, VMOV, VMUL, VNEG, VNMLA, VNMLS, VNMUL, VSQRT, or VSUB instruction when one or both of FPSCR.{Stride, Len} was nonzero. If FPEXC32_EL2.{IDF, IXF, UFF, OFF, DZF, IOF} are RW then they are invalid and UNKNOWN. 0b1 FPEXC32_EL2.{IDF, IXF, UFF, OFF, DZF, IOF} indicate the presence of trapped floating-point exceptions that had occurred at the time of the exception. Bits are set for all trapped exceptions that had occurred at the time of the exception. AU When an implementation does not implement trapping of floating-point exceptions RAZ/WI When an implementation implements FPSCR.{Stride,Len} as RAZ RAO/WI 25 11 25:11 Reserved, RES0. VECITR 10 8 10:8 Vector iteration count. From Armv8, this field is RES1. AU RES1 IDF 7 7 7 Input Denormal trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Input Denormal exception occurred while FPSCR.IDE was 1: Input Denormal exceptions can occur only when FPSCR.FZ is 1. A half-precision floating-point value that is flushed to zero because the value of FPSCR.FZ16 is 1 does not generate an Input Denormal exception.This bit must be cleared to 0 by the exception-handling routine. When the value of FPEXC32_EL2.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN. 0b0 Input Denormal exception has not occurred. 0b1 Input Denormal exception has occurred. AU When an implementation does not implement trapping of Input Denormal floating-point exceptions RAZ/WI 6 5 6:5 Reserved, RES0. IXF 4 4 4 Inexact trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Inexact exception occurred while FPSCR.IXE was 1: This bit must be cleared to 0 by the exception-handling routine. When the value of FPEXC.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN. 0b0 Inexact exception has not occurred. 0b1 Inexact exception has occurred. AU When an implementation does not implement trapping of Inexact floating-point exceptions RAZ/WI UFF 3 3 3 Underflow trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Underflow exception occurred while FPSCR.UFE was 1: Underflow trapped exceptions can occur: On half-precision data-processing instructions only when FPSCR.FZ16 is 0. Otherwise only when FPSCR.FZ is 0. This bit must be cleared to 0 by the exception-handling routine. When the value of FPEXC32_EL2.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN. 0b0 Underflow exception has not occurred. 0b1 Underflow exception has occurred. AU When an implementation does not implement trapping of Underflow floating-point exceptions RAZ/WI OFF 2 2 2 Overflow trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Overflow exception occurred while FPSCR.OFE was 1: This bit must be cleared to 0 by the exception-handling routine. When the value of FPEXC.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN. 0b0 Overflow exception has not occurred. 0b1 Overflow exception has occurred. AU When an implementation does not implement trapping of Overflow floating-point exceptions RAZ/WI DZF 1 1 1 Divide by Zero trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether a Divide by Zero exception occurred while FPSCR.DZE was 1: This bit must be cleared to 0 by the exception-handling routine. When the value of FPEXC.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN. 0b0 Divide by Zero exception has not occurred. 0b1 Divide by Zero exception has occurred. AU When an implementation does not implement trapping of Divide by Zero floating-point exceptions RAZ/WI IOF 0 0 0 Invalid Operation trapped exception bit. Valid only when the value of FPEXC.TFV is 1. When valid, it indicates whether an Invalid Operation exception occurred while FPSCR.IOE was 1: This bit must be cleared to 0 by the exception-handling routine. When the value of FPEXC.TFV is 0 and this bit is RW, this bit is invalid and UNKNOWN. 0b0 Invalid Operation exception has not occurred. 0b1 Invalid Operation exception has occurred. AU When an implementation does not implement trapping of Invalid Operation floating-point exceptions RAZ/WI MRS <Xt>, FPEXC32_EL2 if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else X{64}(t) = FPEXC32_EL2(); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TFP == '1' then AArch64_SystemAccessTrap(EL3, 0x07); else X{64}(t) = FPEXC32_EL2(); end; end; MSR FPEXC32_EL2, <Xt> if !(IsFeatureImplemented(FEAT_AA32EL1) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else FPEXC32_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TFP == '1' then AArch64_SystemAccessTrap(EL3, 0x07); else FPEXC32_EL2() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel