FPMR Floating-point Mode Register when FEAT_FPMR is implemented and FEAT_AA64 is implemented Controls behaviors of the FP8 instructions. Float A direct or indirect read of this register occurs in program order relative to a direct write of this register without explicit synchronization. On entry to or exit from Streaming SVE mode, FPMR is set to 0. FPMR is a 64-bit register. 63 38 63:38 Reserved, RES0. LSCALE2 37 32 37:32 Downscaling value for instructions that convert the second FP8 input data stream to other floating-point formats. This value is an unsigned integer that is subtracted from the result exponent. AU NSCALE 31 24 31:24 Scaling value for instructions that convert other floating-point formats to an FP8 format. This value is a signed integer that is added to the operand exponent. AU 23 23 23 Reserved, RES0. LSCALE 22 16 22:16 Downscaling value. This value is an unsigned integer that is subtracted from: The product or the sum-of-products exponent, for multiplication instructions with FP8 operands. The result exponent, for instructions that convert the first FP8 input data stream to other floating-point formats. AU OSC 15 15 15 Overflow saturation for FP8 convert instructions. Specifies the result when a floating-point Overflow exception is detected. 0b0 Infinity or NaN is generated. 0b1 Maximum normal number is generated. AU OSM 14 14 14 Overflow saturation for FP8 multiplication instructions. Specifies the result when a floating-point Overflow exception is detected. 0b0 Infinity is generated. 0b1 Maximum normal number is generated. AU 13 9 13:9 Reserved, RES0. F8D 8 6 8:6 Destination result format for instructions that convert other floating-point values to an FP8 format. All other values are reserved. Reserved values identify an unsupported format and behave as described in Reserved values in System and memory-mapped registers and translation table entries. Additionally, FP8 instructions are permitted to set an FP8 result with an unsupported format to 0xFF and signal an Invalid Operation floating-point exception. It is software's responsibility to check that a format value is supported in ID_AA64FPFR0_EL1[7:0], before writing it to this field. For more information about the FP8 formats, see the OCP 8-bit Floating Point Specification (OFP8). 0b000 OFP8 E5M2 format. 0b001 OFP8 E4M3 format. AU F8S2 5 3 5:3 Second FP8 input data stream format for multiplication instructions with FP8 operands, and the corresponding instructions that convert an FP8 format to other floating-point formats. All other values are reserved. Reserved values identify an unsupported format and behave as described in Reserved values in System and memory-mapped registers and translation table entries. Additionally FP8 instructions are permitted to treat FP8 input values with an unsupported format as a signaling NaN. It is software's responsibility to check that a format value is supported in ID_AA64FPFR0_EL1[7:0], before writing it to this field. For more information about the FP8 formats, see the OCP 8-bit Floating Point Specification (OFP8). 0b000 OFP8 E5M2 format. 0b001 OFP8 E4M3 format. AU F8S1 2 0 2:0 First FP8 input data stream format for multiplication instructions with FP8 operands, and the corresponding instructions that convert an FP8 format to other floating-point formats. All other values are reserved. Reserved values identify an unsupported format and behave as described in Reserved values in System and memory-mapped registers and translation table entries. Additionally FP8 instructions are permitted to treat FP8 input values with an unsupported format as a signaling NaN. It is software's responsibility to check that a format value is supported in ID_AA64FPFR0_EL1[7:0], before writing it to this field. For more information about the FP8 formats, see the OCP 8-bit Floating Point Specification (OFP8). 0b000 OFP8 E5M2 format. 0b001 OFP8 E4M3 format. AU MRS <Xt>, FPMR if !(IsFeatureImplemented(FEAT_FPMR) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().EnFPM == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif !ELIsInHost(EL0) && SCTLR_EL1().EnFPM == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif ELIsInHost(EL0) && SCTLR_EL2().EnFPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && (!IsHCRXEL2Enabled() || HCRX_EL2().EnFPM == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !ELIsInHost(EL0) && CPACR_EL1().FPEN != '11' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x00); else AArch64_SystemAccessTrap(EL1, 0x07); end; elsif ELIsInHost(EL0) && CPTR_EL2().FPEN != '11' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else X{64}(t) = FPMR(); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().EnFPM == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif EL2Enabled() && !ELIsInHost(EL0) && (!IsHCRXEL2Enabled() || HCRX_EL2().EnFPM == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif CPACR_EL1().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else X{64}(t) = FPMR(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().EnFPM == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else X{64}(t) = FPMR(); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TFP == '1' then AArch64_SystemAccessTrap(EL3, 0x07); else X{64}(t) = FPMR(); end; end; MSR FPMR, <Xt> if !(IsFeatureImplemented(FEAT_FPMR) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().EnFPM == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif !ELIsInHost(EL0) && SCTLR_EL1().EnFPM == '0' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else AArch64_SystemAccessTrap(EL1, 0x18); end; elsif ELIsInHost(EL0) && SCTLR_EL2().EnFPM == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && !ELIsInHost(EL0) && (!IsHCRXEL2Enabled() || HCRX_EL2().EnFPM == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !ELIsInHost(EL0) && CPACR_EL1().FPEN != '11' then if EL2Enabled() && HCR_EL2().TGE == '1' then AArch64_SystemAccessTrap(EL2, 0x00); else AArch64_SystemAccessTrap(EL1, 0x07); end; elsif ELIsInHost(EL0) && CPTR_EL2().FPEN != '11' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else FPMR() = X{64}(t); end; elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().EnFPM == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif EL2Enabled() && !ELIsInHost(EL0) && (!IsHCRXEL2Enabled() || HCRX_EL2().EnFPM == '0') then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif CPACR_EL1().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL1, 0x07); elsif EL2Enabled() && !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else FPMR() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().EnFPM == '0' then Undefined(); elsif HaveEL(EL3) && EL3SDDUndefPriority() && CPTR_EL3().TFP == '1' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().EnFPM == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif !ELIsInHost(EL2) && CPTR_EL2().TFP == '1' then AArch64_SystemAccessTrap(EL2, 0x07); elsif ELIsInHost(EL2) && CPTR_EL2().FPEN IN {'x0'} then AArch64_SystemAccessTrap(EL2, 0x07); elsif HaveEL(EL3) && CPTR_EL3().TFP == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x07); end; else FPMR() = X{64}(t); end; elsif PSTATE.EL == EL3 then if CPTR_EL3().TFP == '1' then AArch64_SystemAccessTrap(EL3, 0x07); else FPMR() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel