<?xml version='1.0' encoding='utf-8'?>
<!DOCTYPE register_page SYSTEM "registers.dtd">
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<register_page>
  <registers>
  
    <register execution_state="AArch64" is_register="False" is_internal="True" is_stub_entry="False">
      <reg_short_name>GCSPOPCX</reg_short_name>
        
        <reg_long_name>Guarded Control Stack Pop and Compare exception return record</reg_long_name>



      
            <reg_condition otherwise="UNDEFINED">when FEAT_GCS is implemented and FEAT_AA64 is implemented</reg_condition>
      




          <reg_reset_value></reg_reset_value>

      <reg_mappings>
        




      </reg_mappings>

        <reg_purpose>
          
    
      <purpose_text>
        <para>Loads a GCS exception return record from the location indicated by the current GCS pointer register, compares the values loaded with the current ELR_ELx, SPSR_ELx, and LR, and increments the current GCS pointer register by the size of a GCS exception return record.</para>
      </purpose_text>

        </reg_purpose>

      <reg_groups>
            <reg_group>GCSE Instructions</reg_group>
      </reg_groups>
      
      
        
      <reg_attributes>
          
    
      <attributes_text>
        <para>GCSPOPCX is a 64-bit System instruction.</para>
      </attributes_text>

      </reg_attributes>
      <reg_fieldsets>
        







      </reg_fieldsets>

      <access_mechanisms>
          


  
    
      <access_permission_text>
        <para>Rt should be encoded as <binarynumber>0b11111</binarynumber>. If the Rt field is not set to <binarynumber>0b11111</binarynumber>, it is <arm-defined-word>CONSTRAINED UNPREDICTABLE</arm-defined-word> whether:</para>

      </access_permission_text>
      <access_permission_text>
        <list type="unordered">
<listitem><content>
<para>The instruction is <arm-defined-word>UNDEFINED</arm-defined-word>.</para>
</content>
</listitem><listitem><content>
<para>The instruction behaves as if the Rt field is set to <binarynumber>0b11111</binarynumber>.</para>
</content>
</listitem></list>

      </access_permission_text>
      <access_permission_text>
        <para>This system instruction is an alias of the SYS instruction.</para>
      </access_permission_text>





    
        
        <access_mechanism accessor="GCSPOPCX" type="SystemAccessor">
            <encoding>
            <access_instruction>GCSPOPCX</access_instruction>
                
                <enc n="op0" v="0b01"/>
                
                <enc n="op1" v="0b000"/>
                
                <enc n="CRn" v="0b0111"/>
                
                <enc n="CRm" v="0b0111"/>
                
                <enc n="op2" v="0b101"/>
            </encoding>
            <access_permission>
                <ps name="GCSPOPCX" sections="1" secttype="access_permission">
                <pstext>
if !(IsFeatureImplemented(FEAT_GCS) &amp;&amp; IsFeatureImplemented(FEAT_AA64)) then
    Undefined();
elsif PSTATE.EL == EL0 then
    Undefined();
elsif PSTATE.EL == EL1 then
    if IsFeatureImplemented(FEAT_GCS) &amp;&amp; GetCurrentEXLOCKEN() &amp;&amp; !Halted() &amp;&amp; PSTATE.EXLOCK == '1' then
        EXLOCKException();
    elsif EL2Enabled() &amp;&amp; IsFeatureImplemented(FEAT_FGT) &amp;&amp; (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') &amp;&amp; HFGITR_EL2().nGCSEPP == '0' then
        AArch64_SystemAccessTrap(EL2, 0x18);
    elsif GCSEnabled(EL1) then
        GCSPOPCX();
    end;
elsif PSTATE.EL == EL2 then
    if IsFeatureImplemented(FEAT_GCS) &amp;&amp; GetCurrentEXLOCKEN() &amp;&amp; !Halted() &amp;&amp; PSTATE.EXLOCK == '1' then
        EXLOCKException();
    elsif GCSEnabled(EL2) then
        GCSPOPCX();
    end;
elsif PSTATE.EL == EL3 then
    if IsFeatureImplemented(FEAT_GCS) &amp;&amp; GetCurrentEXLOCKEN() &amp;&amp; !Halted() &amp;&amp; PSTATE.EXLOCK == '1' then
        EXLOCKException();
    elsif GCSEnabled(EL3) then
        GCSPOPCX();
    end;
end;
                </pstext>
                </ps>
            </access_permission>
        </access_mechanism>

      </access_mechanisms>

      <arch_variants>
      </arch_variants>
  </register>
</registers>
<timestamp>2026-03-26 20:27:25</timestamp>
<commit_id>2026-03_rel</commit_id>
</register_page>