GCSPR_EL1 Guarded Control Stack Pointer Register (EL1) when FEAT_GCS is implemented Contains the Guarded Control Stack Pointer at EL1. Guarded Control Stack registers GCSPR_EL1 is a 64-bit register. PTR[63:3] 63 3 63:3 EL1 Guarded Control Stack Pointer bits [63:3]. AU 2 0 2:0 Reserved, RES0. When the Effective value of HCR_EL2.E2H is 1, without explicit synchronization, accesses from EL3 using the accessor name GCSPR_EL1 or GCSPR_EL12 are not guaranteed to be ordered with respect to accesses using the other accessor name. MRS <Xt>, GCSPR_EL1 if !IsFeatureImplemented(FEAT_GCS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().GCSEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().nGCS_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().GCSEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then X{64}(t) = NVMem(0x8C0); else X{64}(t) = GCSPR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().GCSEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().GCSEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then X{64}(t) = GCSPR_EL2(); else X{64}(t) = GCSPR_EL1(); end; elsif PSTATE.EL == EL3 then X{64}(t) = GCSPR_EL1(); end; MSR GCSPR_EL1, <Xt> if !IsFeatureImplemented(FEAT_GCS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().GCSEn == '0' then Undefined(); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().nGCS_EL1 == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().GCSEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif EffectiveHCR_EL2_NVx() IN {'111'} then NVMem(0x8C0) = X{64}(t); else GCSPR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().GCSEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().GCSEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif ELIsInHost(EL2) then GCSPR_EL2() = X{64}(t); else GCSPR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then GCSPR_EL1() = X{64}(t); end; MRS <Xt>, GCSPR_EL12 When FEAT_VHE is implemented if !IsFeatureImplemented(FEAT_GCS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then X{64}(t) = NVMem(0x8C0); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().GCSEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().GCSEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = GCSPR_EL1(); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then X{64}(t) = GCSPR_EL1(); else Undefined(); end; end; MSR GCSPR_EL12, <Xt> When FEAT_VHE is implemented if !IsFeatureImplemented(FEAT_GCS) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() == '101' then NVMem(0x8C0) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ELIsInHost(EL2) then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().GCSEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().GCSEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else GCSPR_EL1() = X{64}(t); end; else Undefined(); end; elsif PSTATE.EL == EL3 then if ELIsInHost(EL2) then GCSPR_EL1() = X{64}(t); else Undefined(); end; end; 2026-03-26 20:27:25 2026-03_rel