GPCBW_EL3
Granule Protection Check Bypass Window Register (EL3)
when FEAT_RME_GPC3 is implemented and FEAT_AA64 is implemented
The control register for Granule Protection Check bypass window.
Memory
Root
GPCBW_EL3 is a 64-bit register.
63
40
63:40
Reserved, RES0.
BWSIZE
39
37
39:37
GPC Bypass Window Size.
BWSIZE defines the size of the GPC bypass memory region.
All other values are reserved.
This field is permitted to be cached in a TLB.
0b000
30 bits, 1GB GPC bypass window.
0b001
31 bits, 2GB GPC bypass window.
0b010
32 bits, 4GB GPC bypass window.
0b100
34 bits, 16GB GPC bypass window.
0b110
36 bits, 64GB GPC bypass window.
AU
BWSTRIDE
36
32
36:32
GPC Bypass Window Stride.
BWSTRIDE allows creating multiple GPC bypass memory regions in the memory map across a specific stride.
All other values are reserved.
This field is permitted to be cached in a TLB.
0b00000
1TB stride.
0b00010
4TB stride.
0b00100
16TB stride.
0b00110
64TB stride.
0b00111
128TB stride.
0b01000
256TB stride.
0b01001
512TB stride.
0b01010
1PB stride.
0b10000
64PB (No stride).
AU
31
26
31:26
Reserved, RES0.
BWADDR
25
0
25:0
GPC Bypass window address.
This field represents bits [55:30] of the GPC bypass window base address.
The GPC bypass window is:
Aligned in memory to the size of the window as specified by GPCBW_EL3.BWSIZE.
Duplicated in PA space across a stride specified using GPCBW_EL3.BWSTRIDE.
This means that only bits [gpcbwu:gpcbwl] of a PA are compared against bits [gpcbwu:gpcbwl] of the window base address derived from BWADDR when checking if a PA falls within the range of a window, where:
gpcbwl is derived from GPCBW_EL3.BWSIZE as follows:
BWSIZEgpcbwl
0b00030
0b00131
0b01032
0b10034
0b11036
gpcbwu is derived from GPCBW_EL3.BWSTRIDE as follows:
BWSTRIDEgpcbwu
0b0000039
0b0001041
0b0010043
0b0011045
0b0011146
0b0100047
0b0100148
0b0101049
0b1000055
If the base address derived from BWADDR is not aligned to the size programmed in BWSIZE the configuration is invalid.
If this field is configured to a value that produces a GPC bypass window base address that is greater than or equal to the stride value configured by BWSTRIDE, the configuration is invalid.
An access to a PA falls within a GPC bypass window if the pseudocode function PAWithinGPCBypassWindow() returns TRUE.
This field is permitted to be cached in a TLB.
AU
MRS <Xt>, GPCBW_EL3
if !(IsFeatureImplemented(FEAT_RME_GPC3) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
Undefined();
elsif PSTATE.EL == EL2 then
Undefined();
elsif PSTATE.EL == EL3 then
X{64}(t) = GPCBW_EL3();
end;
MSR GPCBW_EL3, <Xt>
if !(IsFeatureImplemented(FEAT_RME_GPC3) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
Undefined();
elsif PSTATE.EL == EL2 then
Undefined();
elsif PSTATE.EL == EL3 then
if IsFeatureImplemented(FEAT_FGWTE3) && FGWTE3_EL3().GPCBW_EL3 == '1' then
AArch64_SystemAccessTrap(EL3, 0x18);
else
GPCBW_EL3() = X{64}(t);
end;
end;
2026-03-26 20:27:25
2026-03_rel