GPCCR_EL3
Granule Protection Check Control Register (EL3)
when FEAT_RME is implemented and FEAT_AA64 is implemented
The control register for Granule Protection Checks.
Memory
Root
GPCCR_EL3 is a 64-bit register.
63
30
63:30
Reserved, RES0.
GPCBW
29
29
0
GPC Bypass Window Enable.
This field governs the behavior of the GPC bypass windows.
This bit is permitted to be cached in a TLB.
0b0
GPC bypass windows are disabled.
0b1
GPC bypass windows are enabled.
AU
When FEAT_RME_GPC3 is implemented
29
29
29
Reserved, RES0.
Otherwise
NA7
28
28
0
No access 7.
This field governs the behavior of the GPI encoding for NA7.
This bit is permitted to be cached in a TLB.
0b0
GPI encoding value of 0b0111 is reserved.
0b1
GPI encoding value of 0b0111 is No access permitted from this PE.
AU
When FEAT_RME_GDI is implemented
28
28
28
Reserved, RES0.
Otherwise
NA6
27
27
0
No access 6.
This field governs the behavior of the GPI encoding for NA6.
This bit is permitted to be cached in a TLB.
0b0
GPI encoding value of 0b0110 is reserved.
0b1
GPI encoding value of 0b0110 is No access permitted from this PE.
AU
When FEAT_RME_GDI is implemented
27
27
27
Reserved, RES0.
Otherwise
NSP
26
26
0
Non-secure Protected.
This field governs the behavior of the GPI encoding for NSP.
This bit is permitted to be cached in a TLB.
0b0
GPI encoding value of 0b0101 is reserved.
0b1
GPI encoding value of 0b0101 is No access permitted from this PE.
AU
When FEAT_RME_GDI is implemented
26
26
26
Reserved, RES0.
Otherwise
SA
25
25
0
System Agent.
This field governs the behavior of the GPI encoding for SA.
This bit is permitted to be cached in a TLB.
0b0
GPI encoding value of 0b0100 is reserved.
0b1
GPI encoding value of 0b0100 is No access permitted from this PE.
AU
When FEAT_RME_GDI is implemented
25
25
25
Reserved, RES0.
Otherwise
APPSAA
24
24
0
Above PPS All Access. This field governs the behavior of memory accesses to Secure, Realm and Root PA space, for physical addresses above the range configured by GPCCR_EL3.PPS.
This bit is permitted to be cached in a TLB.
0b0
Accesses to addresses above the configured PPS must be to Non-secure PA space, otherwise they generate a GPF at level 0.
0b1
Accesses to addresses above the configured PPS, to any PA space, do not generate a GPF because of this control.
AU
When FEAT_RME_GPC2 is implemented
24
24
24
Reserved, RES0.
Otherwise
L0GPTSZ
23
20
23:20
Level 0 GPT entry size.
This field advertises the number of least-significant address bits protected by each entry in the level 0 GPT.
All other values are reserved.
0b0000
30-bits. Each entry covers 1GB of address space.
0b0100
34-bits. Each entry covers 16GB of address space.
0b0110
36-bits. Each entry covers 64GB of address space.
0b1001
39-bits. Each entry covers 512GB of address space.
RO
NSO
19
19
0
Non-secure Only. This field governs the behavior of the GPI encoding for NSO.
This bit is permitted to be cached in a TLB.
0b0
GPI encoding value of 0b1101 is reserved.
0b1
GPI encoding value of 0b1101 is NSO.
AU
When FEAT_RME_GPC2 is implemented
19
19
19
Reserved, RES0.
Otherwise
TBGPCD
18
18
0
Trace Buffer Granule Protection Check Disabled. Controls whether the Trace Buffer Unit accepts or rejects trace when Granule Protection Checks are disabled.
When the Trace Buffer Unit rejects trace, the trace might remain buffered by the trace unit until the Trace Buffer Unit is able to accept trace. When the Trace Buffer Unit accepts trace, the Trace Buffer Unit writes the trace to memory.
Setting GPCCR_EL3.{TBGPCD, GPC} to {1, 0} means that the Trace Buffer Unit might write to memory without any Granule Protection Checks. The addresses that the Trace Buffer Unit writes to can be programmed by an external agent. The physical address spaces the Trace Buffer Unit can address are restricted by an IMPLEMENTATION DEFINED debug authentication interface.Setting GPCCR_EL3.{TBGPCD, GPC} to {1, 1} means that GPCCR_EL3.{TBGPCD, GPC} will become {1, 0} on a Warm reset.This field is ignored by the PE and treated as one when any of the following are true:
GPCCR_EL3.GPC == 1.
ExternalRootInvasiveDebugEnabled() == TRUE.
0b0
The Trace Buffer Unit rejects trace when GPCCR_EL3.GPC is 0.
0b1
The Trace Buffer Unit accepts trace when GPCCR_EL3.GPC is 0.
'0'
When FEAT_TRBE_EXT is implemented
18
18
18
Reserved, RES0.
Otherwise
GPCP
17
17
17
Granule Protection Check Priority.
This control governs behavior of granule protection checks on fetches of stage 2 Table descriptors.
This bit is permitted to be cached in a TLB.
An implementation is permitted to treat this field as RES0, with an Effective value of 0.
0b0
GPC faults are all reported with a priority that is consistent with the GPC being performed on any access to physical address space.
0b1
A GPC fault for the fetch of a Table descriptor for a stage 2 translation table walk might not be generated or reported.
All other GPC faults are reported with a priority consistent with the GPC being performed on all accesses to physical address spaces.
AU
GPC
16
16
16
Granule Protection Check Enable.
If any stage of translation is enabled, this bit is permitted to be cached in a TLB.
0b0
Granule protection checks are disabled. Accesses are not prevented by this mechanism.
0b1
All accesses to physical address spaces are subject to granule protection checks, except for fetches of GPT information and accesses governed by the GPCCR_EL3.GPCP control.
'0'
PGS
15
14
15:14
Physical Granule size.
All other values are reserved.
The value of this field is permitted to be cached in a TLB.
Granule sizes not supported for stage 1 and not supported for stage 2, as defined in ID_AA64MMFR0_EL1, are reserved. For example, if ID_AA64MMFR0_EL1.TGran16 == 0b0000 and ID_AA64MMFR0_EL1.TGran16_2 == 0b0001, then the PGS encoding 0b10 is reserved.
0b00
4KB.
0b01
64KB.
0b10
16KB.
AU
SH
13
12
13:12
GPT fetch Shareability attribute
All other values are reserved.
Fetches of GPT information are made with the Shareability attribute that is configured in this field.
If both ORGN and IRGN are configured with Non-cacheable attributes, it is invalid to configure this field to any value other than 0b10.
0b00
Non-shareable.
0b10
Outer Shareable.
0b11
Inner Shareable.
AU
ORGN
11
10
11:10
GPT fetch Outer cacheability attribute.
Fetches of GPT information are made with the Outer cacheability attributes configured in this field.
0b00
Normal memory, Outer Non-cacheable.
0b01
Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable.
0b10
Normal memory, Outer Write-Through Read-Allocate No Write-Allocate Cacheable.
0b11
Normal memory, Outer Write-Back Read-Allocate No Write-Allocate Cacheable.
AU
IRGN
9
8
9:8
GPT fetch Inner cacheability attribute.
Fetches of GPT information are made with the Inner cacheability attributes configured in this field.
0b00
Normal memory, Inner Non-cacheable.
0b01
Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable.
0b10
Normal memory, Inner Write-Through Read-Allocate No Write-Allocate Cacheable.
0b11
Normal memory, Inner Write-Back Read-Allocate No Write-Allocate Cacheable.
AU
SPAD
7
7
0
Secure PA space Disable. This field controls access to the Secure PA space.
This bit is permitted to be cached in a TLB.
0b0
This control has no effect on accesses.
0b1
When granule protection checks are enabled, access to the Secure Physical Address space generates a Granule Protection fault.
AU
When FEAT_RME_GPC2 is implemented
7
7
7
Reserved, RES0.
Otherwise
NSPAD
6
6
0
Non-secure PA space Disable. This field controls access to the Non-secure PA space.
This bit is permitted to be cached in a TLB.
0b0
This control has no effect on accesses.
0b1
When granule protection checks are enabled, access to the Non-secure Physical Address space generates a Granule Protection fault.
AU
When FEAT_RME_GPC2 is implemented
6
6
6
Reserved, RES0.
Otherwise
RLPAD
5
5
0
Realm PA space Disable. This field controls access to the Realm PA space.
This bit is permitted to be cached in a TLB.
0b0
This control has no effect on accesses.
0b1
When granule protection checks are enabled, access to the Realm Physical Address space generates a Granule Protection fault.
AU
When FEAT_RME_GPC2 is implemented
5
5
5
Reserved, RES0.
Otherwise
4
4
4
Reserved, RES0.
PPS3
3
3
0
This field extends GPCCR_EL3.PPS[2:0], creating a GPCCR_EL3.PPS[3:0] field.
For a description of the values derived by evaluating PPS, see GPCCR_EL3.PPS[2:0].
The value of this field is permitted to be cached in a TLB.
AU
When FEAT_RME_GPC3 is implemented
3
3
3
Reserved, RES0.
Otherwise
PPS
2
0
2:0
Protected Physical Address Size.
The size of the memory region protected by GPTBR_EL3, in terms of the number of least-significant address bits.
This field is evaluated with PPS3, as {PPS3, PPS} to give PPS[3:0], interpreted as:
PPS[3:0]Meaning
0b000032 bits, 4GB protected address space.
0b000136 bits, 64GB protected address space.
0b001040 bits, 1TB protected address space.
0b001142 bits, 4TB protected address space.
0b010044 bits, 16TB protected address space.
0b100046 bits, 64TB protected address space.
0b100147 bits, 128TB protected address space.
0b010148 bits, 256TB protected address space.
0b011052 bits, 4PB protected address space.
0b011156 bits, 64PB protected address space.
All other values are reserved.
Configuration of this field to a value exceeding the implemented physical address size is invalid.
The value of this field is permitted to be cached in a TLB.
AU
When FEAT_RME_GPC3 is implemented
PPS
2
0
2:0
Protected Physical Address Size.
The size of the memory region protected by GPTBR_EL3, in terms of the number of least-significant address bits.
All other values are reserved.
Configuration of this field to a value exceeding the implemented physical address size is invalid.
The value of this field is permitted to be cached in a TLB.
0b000
32 bits, 4GB protected address space.
0b001
36 bits, 64GB protected address space.
0b010
40 bits, 1TB protected address space.
0b011
42 bits, 4TB protected address space.
0b100
44 bits, 16TB protected address space.
0b101
48 bits, 256TB protected address space.
0b110
52 bits, 4PB protected address space.
AU
Otherwise
MRS <Xt>, GPCCR_EL3
if !(IsFeatureImplemented(FEAT_RME) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
Undefined();
elsif PSTATE.EL == EL2 then
Undefined();
elsif PSTATE.EL == EL3 then
X{64}(t) = GPCCR_EL3();
end;
MSR GPCCR_EL3, <Xt>
if !(IsFeatureImplemented(FEAT_RME) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
Undefined();
elsif PSTATE.EL == EL2 then
Undefined();
elsif PSTATE.EL == EL3 then
if IsFeatureImplemented(FEAT_FGWTE3) && FGWTE3_EL3().GPCCR_EL3 == '1' then
AArch64_SystemAccessTrap(EL3, 0x18);
else
GPCCR_EL3() = X{64}(t);
end;
end;
2026-03-26 20:27:25
2026-03_rel