HAFGRTR_EL2 Hypervisor Activity Monitors Fine-Grained Read Trap Register when FEAT_AMUv1 is implemented, FEAT_FGT is implemented, and FEAT_AA64 is implemented Provides controls for traps of MRS reads of Activity Monitors System registers. Unknown If EL2 is not implemented, this register is RES0 from EL3. HAFGRTR_EL2 is a 64-bit register. 63 50 63:50 Reserved, RES0. AMEVTYPER1<x>_EL0 49 49 49, 47, 45, 43, 41, 39, 37, 35, 33, 31, 29, 27, 25, 23, 21, 19 Trap MRS reads of AMEVTYPER1<x>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER1<x> at EL0 using AArch32 when EL1 is using AArch64 to EL2. 49 49 47 47 45 45 43 43 41 41 39 39 37 37 35 35 33 33 31 31 29 29 27 27 25 25 23 23 21 21 19 19 15 0 AMEVTYPER1<x>_EL0 0b0 MRS reads of AMEVTYPER1<x>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER1<x> at EL0 using AArch32 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception: MRS reads of AMEVTYPER1<x>_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRC reads of AMEVTYPER1<x> at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03. '0' AU When x >= UInt(AMCGCR_EL0.CG1NC) RES0 When !IsG1ActivityMonitorImplemented(x) RES0 AMEVTYPER115_EL0 49 49 15 Trap MRS reads of AMEVTYPER115_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER115 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVCNTR1<x>_EL0 48 48 48, 46, 44, 42, 40, 38, 36, 34, 32, 30, 28, 26, 24, 22, 20, 18 Trap MRS reads of AMEVCNTR1<x>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR1<x> at EL0 using AArch32 when EL1 is using AArch64 to EL2. 48 48 46 46 44 44 42 42 40 40 38 38 36 36 34 34 32 32 30 30 28 28 26 26 24 24 22 22 20 20 18 18 15 0 AMEVCNTR1<x>_EL0 0b0 MRS reads of AMEVCNTR1<x>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR1<x> at EL0 using AArch32 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception: MRS reads of AMEVCNTR1<x>_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRC reads of AMEVCNTR1<x> at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03. '0' AU When x >= UInt(AMCGCR_EL0.CG1NC) RES0 When !IsG1ActivityMonitorImplemented(x) RES0 AMEVCNTR115_EL0 48 48 15 Trap MRS reads of AMEVCNTR115_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR115 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVTYPER114_EL0 47 47 14 Trap MRS reads of AMEVTYPER114_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER114 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVCNTR114_EL0 46 46 14 Trap MRS reads of AMEVCNTR114_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR114 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVTYPER113_EL0 45 45 13 Trap MRS reads of AMEVTYPER113_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER113 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVCNTR113_EL0 44 44 13 Trap MRS reads of AMEVCNTR113_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR113 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVTYPER112_EL0 43 43 12 Trap MRS reads of AMEVTYPER112_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER112 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVCNTR112_EL0 42 42 12 Trap MRS reads of AMEVCNTR112_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR112 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVTYPER111_EL0 41 41 11 Trap MRS reads of AMEVTYPER111_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER111 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVCNTR111_EL0 40 40 11 Trap MRS reads of AMEVCNTR111_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR111 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVTYPER110_EL0 39 39 10 Trap MRS reads of AMEVTYPER110_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER110 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVCNTR110_EL0 38 38 10 Trap MRS reads of AMEVCNTR110_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR110 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVTYPER19_EL0 37 37 9 Trap MRS reads of AMEVTYPER19_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER19 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVCNTR19_EL0 36 36 9 Trap MRS reads of AMEVCNTR19_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR19 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVTYPER18_EL0 35 35 8 Trap MRS reads of AMEVTYPER18_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER18 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVCNTR18_EL0 34 34 8 Trap MRS reads of AMEVCNTR18_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR18 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVTYPER17_EL0 33 33 7 Trap MRS reads of AMEVTYPER17_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER17 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVCNTR17_EL0 32 32 7 Trap MRS reads of AMEVCNTR17_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR17 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVTYPER16_EL0 31 31 6 Trap MRS reads of AMEVTYPER16_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER16 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVCNTR16_EL0 30 30 6 Trap MRS reads of AMEVCNTR16_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR16 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVTYPER15_EL0 29 29 5 Trap MRS reads of AMEVTYPER15_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER15 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVCNTR15_EL0 28 28 5 Trap MRS reads of AMEVCNTR15_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR15 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVTYPER14_EL0 27 27 4 Trap MRS reads of AMEVTYPER14_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER14 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVCNTR14_EL0 26 26 4 Trap MRS reads of AMEVCNTR14_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR14 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVTYPER13_EL0 25 25 3 Trap MRS reads of AMEVTYPER13_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER13 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVCNTR13_EL0 24 24 3 Trap MRS reads of AMEVCNTR13_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR13 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVTYPER12_EL0 23 23 2 Trap MRS reads of AMEVTYPER12_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER12 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVCNTR12_EL0 22 22 2 Trap MRS reads of AMEVCNTR12_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR12 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVTYPER11_EL0 21 21 1 Trap MRS reads of AMEVTYPER11_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER11 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVCNTR11_EL0 20 20 1 Trap MRS reads of AMEVCNTR11_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR11 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVTYPER10_EL0 19 19 0 Trap MRS reads of AMEVTYPER10_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVTYPER10 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMEVCNTR10_EL0 18 18 0 Trap MRS reads of AMEVCNTR10_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR10 at EL0 using AArch32 when EL1 is using AArch64 to EL2. AMCNTEN<x> 17 17 17, 0 Trap MRS reads and MRC reads of multiple System registers. Enables a trap to EL2 the following operations: At EL1 and EL0 using AArch64: MRS reads of AMCNTENCLR<x>_EL0 and AMCNTENSET<x>_EL0. At EL0 using AArch32 when EL1 is using AArch64: MRC reads of AMCNTENCLR<x> and AMCNTENSET<x>. 17 17 0 0 1 0 AMCNTEN<x> 0b0 The operations listed above are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception: MRS reads at EL1 and EL0 using AArch64 of AMCNTENCLR<x>_EL0 and AMCNTENSET<x>_EL0 are trapped to EL2 and reported with EC syndrome value 0x18. MRC reads at EL0 using AArch32 of AMCNTENCLR<x> and AMCNTENSET<x> are trapped to EL2 and reported with EC syndrome value 0x03. '0' AU AMCNTEN1 17 17 1 Trap MRS reads and MRC reads of multiple System registers. Enables a trap to EL2 the following operations: At EL1 and EL0 using AArch64: MRS reads of AMCNTENCLR1_EL0 and AMCNTENSET1_EL0. At EL0 using AArch32 when EL1 is using AArch64: MRC reads of AMCNTENCLR1 and AMCNTENSET1. 16 5 16:5 Reserved, RES0. AMEVCNTR0<x>_EL0 4 1 4:1 Trap MRS reads of AMEVCNTR0<x>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR0<x> at EL0 using AArch32 when EL1 is using AArch64 to EL2. 3 0 0b0 MRS reads of AMEVCNTR0<x>_EL0 at EL1 and EL0 using AArch64 and MRC reads of AMEVCNTR0<x> at EL0 using AArch32 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, EL1 is using AArch64, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then, unless the read generates a higher priority exception: MRS reads of AMEVCNTR0<x>_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRC reads of AMEVCNTR0<x> at EL0 using AArch32 are trapped to EL2 and reported with EC syndrome value 0x03. '0' AU When x >= 4 RES0 AMCNTEN0 0 0 0 Trap MRS reads and MRC reads of multiple System registers. Enables a trap to EL2 the following operations: At EL1 and EL0 using AArch64: MRS reads of AMCNTENCLR0_EL0 and AMCNTENSET0_EL0. At EL0 using AArch32 when EL1 is using AArch64: MRC reads of AMCNTENCLR0 and AMCNTENSET0. MRS <Xt>, HAFGRTR_EL2 if !(IsFeatureImplemented(FEAT_AMUv1) && IsFeatureImplemented(FEAT_FGT) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x1E8); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = HAFGRTR_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = HAFGRTR_EL2(); end; MSR HAFGRTR_EL2, <Xt> if !(IsFeatureImplemented(FEAT_AMUv1) && IsFeatureImplemented(FEAT_FGT) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x1E8) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else HAFGRTR_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then HAFGRTR_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel