HCRX_EL2 Extended Hypervisor Configuration Register when FEAT_HCX is implemented and FEAT_AA64 is implemented Provides configuration controls for virtualization, including defining whether various operations are trapped to EL2. Virt If EL2 is not implemented, this register is RES0 from EL3. HCRX_EL2 is a 64-bit register. 63 27 63:27 Reserved, RES0. SRMASKEn 26 26 0 If EL1 is using AArch64, accesses to the following registers are trapped to EL2 and reported using EC syndrome value 0x18: CPACRMASK_EL1. SCTLRMASK_EL1. SCTLR2MASK_EL1. TCRMASK_EL1. TCR2MASK_EL1. ACTLRMASK_EL1, if it is implemented. Traps generated by this control have a lower priority than traps generated by the HFGRTR2_EL2 and HFGWTR2_EL2 controls. When EL2 is not implemented or not enabled in the current Security state, the Effective value of this field is 1. Otherwise, when the Effective value of SCR_EL3.HXEn is 0, the Effective value of this field is 0. 0b0 EL1 accesses to the specified EL1 registers are trapped to EL2. The values in the registers are treated as 0. 0b1 This control does not cause any instructions to be trapped. '0' AU When FEAT_SRMASK is implemented 26 26 26 Reserved, RES0. Otherwise 25 25 25 Reserved, RES0. PACMEn 24 24 0 PACM Enable. Controls the effect of a PACM instruction at EL1 and EL0. The Effective value of this field is 1 when any of the following are true: EL2 is not implemented or not enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. The Effective value of this field is 0 when all of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}. The Effective value of SCR_EL3.HXEn is 0. 0b0 The effects of PACM are disabled at EL1 and EL0, regardless of the value in any other controls. 0b1 This control does not disable the effect of PACM at EL1 and EL0. '0' AU When FEAT_PAuth_LR is implemented 24 24 24 Reserved, RES0. Otherwise EnFPM 23 23 0 Enables direct and indirect accesses to FPMR from EL0 and EL1. When accesses to FPMR are disabled by this control: Direct accesses to FPMR from EL0 and EL1 are trapped to EL2 and reported using EC syndrome value 0x18. Execution of FP8 data-processing instructions that indirectly access FPMR is UNDEFINED at EL0 and EL1. Traps are not taken if there is a higher priority exception generated by the access. The Effective value of this field is 1 when any of the following are true: EL2 is not implemented or not enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. The Effective value of this field is 0 when all of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}. The Effective value of SCR_EL3.HXEn is 0. 0b0 Direct and indirect accesses to FPMR are disabled at EL1 and EL0. 0b1 This control does not cause any instructions to be trapped. '0' AU When FEAT_FPMR is implemented 23 23 23 Reserved, RES0. Otherwise GCSEn 22 22 0 Guarded Control Stack enable. Controls Guarded Control Stack behavior at EL1 and EL0. The Effective value of this field is 1 when any of the following are true: EL2 is not implemented or not enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. The Effective value of this field is 0 when all of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}. The Effective value of SCR_EL3.HXEn is 0. 0b0 The Guarded Control Stack is disabled at EL1 and EL0. 0b1 Guarded Control Stack behavior at EL1 and EL0 is not affected by mechanism. '0' AU When FEAT_GCS is implemented 22 22 22 Reserved, RES0. Otherwise EnIDCP128 21 21 0 Enables access to IMPLEMENTATION DEFINED 128-bit System registers. The Effective value of this field is 1 when any of the following are true: EL2 is not implemented or not enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. The Effective value of this field is 0 when all of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}. The Effective value of SCR_EL3.HXEn is 0. 0b0 Accesses at EL1, EL0 to IMPLEMENTATION DEFINED 128-bit System registers are trapped to EL2 using EC syndrome value 0x14, unless the access generates a higher priority exception. Disables the functionality of the 128-bit IMPLEMENTATION DEFINED System registers that are accessible at EL2. 0b1 No accesses are trapped by this control. '0' AU When FEAT_SYSREG128 is implemented 21 21 21 Reserved, RES0. Otherwise EnSDERR 20 20 0 Enable Synchronous Device Read Error. Override SCTLR2_EL1.EnADERR. Implementation-specific exceptions to applications of this field are described in 'Taking error exceptions'. Setting this field to 1 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Device memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate. If FEAT_SVE is implemented, HCRX_EL2.EnSDERR is 1, and the access generating the External abort is due to any Active element of an SVE Non-fault vector load instruction or an Active element that is not the First active element of an SVE First-fault vector load instruction, then no exception is generated and the External abort is reported in the FFR. Setting this field to 1 might have a performance impact for Device memory reads. This field is ignored by the PE and has an Effective value of 0 when any of the following are true: All of the following are true: FEAT_ANERR is implemented. ID_AA64MMFR3_EL1.ADERR reads as 0b0010. HCRX_EL2.{EnSDERR, EnSNERR} == {1, 0}. The Effective value of SCR_EL3.HXEn is 0. The Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. EL2 is not implemented or not enabled in the current Security state. 0b0 This field has no effect on External aborts on Device memory reads in the EL1&0 translation regime. 0b1 External abort on Device memory reads generate synchronous Data Abort exceptions in the EL1&0 translation regime. '0' AU When FEAT_ADERR is implemented 20 20 20 Reserved, RES0. Otherwise TMEA 19 19 0 Trap Masked External Aborts. Controls whether a masked error exception at a lower Exception level is taken to EL2. The Effective value of this field is 0 when any of the following are true: The Effective value of SCR_EL3.HXEn is 0. The Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. EL2 is not implemented or not enabled in the current Security state. Virtual SError exceptions are disabled when the Effective value of HCR_EL2.AMO is 0 and the Effective value of HCRX_EL2.TMEA is 0. 0b0 Synchronous External abort exceptions, physical SError exceptions, and delegated SError exceptions at EL1 and EL0 are unaffected by this mechanism. That is, these exceptions are not taken to EL2 unless routed to EL2 by another control. Virtual SError exceptions are not enabled by this mechanism. 0b1 When executing at Exception levels below EL2, if EL2 is enabled in the current Security state, then all of the following apply: When PSTATE.A is 1, synchronous External abort exceptions are taken to EL2, unless they are routed to EL3. Masked physical SError exceptions are taken to EL2, unless they are routed to EL3. If FEAT_E3DSE is implemented, then masked delegated SError exceptions enabled by SCR_EL3.DSE are taken to EL2. If HCR_EL2.TGE is 0, then virtual SError exceptions are enabled. '0' AU When FEAT_DoubleFault2 is implemented 19 19 19 Reserved, RES0. Otherwise EnSNERR 18 18 0 Enable Synchronous Normal Read Error. Override SCTLR2_EL1.EnANERR. Implementation-specific exceptions to applications of this field are described in 'Taking error exceptions'. Setting this field to 1 does not guarantee that the PE is able to take a synchronous Data Abort exception for an External abort on a Normal memory read in every case. There might be implementation-specific circumstances when an error on a load cannot be taken synchronously. These circumstances should be rare enough that treating such occurrences as fatal does not cause a significant increase in failure rate. If FEAT_SVE is implemented, HCRX_EL2.EnSNERR is 1, and the access generating the External abort is due to any Active element of an SVE Non-fault vector load instruction or an Active element that is not the First active element of an SVE First-fault vector load instruction, then no exception is generated and the External abort is reported in the FFR. Setting this field to 1 might have a performance impact for Normal memory reads. This field is ignored by the PE and has an Effective value of 0 when any of the following are true: All of the following are true: FEAT_ADERR is implemented. ID_AA64MMFR3_EL1.ANERR reads as 0b0010. HCRX_EL2.{EnSDERR, EnSNERR} == {0, 1}. The Effective value of SCR_EL3.HXEn is 0. The Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. EL2 is not implemented or not enabled in the current Security state. 0b0 This field has no effect on External aborts on Normal memory reads in the EL1&0 translation regime. 0b1 External abort on Normal memory reads generate synchronous Data Abort exceptions in the EL1&0 translation regime. '0' AU When FEAT_ANERR is implemented 18 18 18 Reserved, RES0. Otherwise D128En 17 17 0 128-bit System Register trap control. Enable access to 128-bit System Registers that relate to VMSAv9-128 via MRRS, MSRR instructions. If EL1 is using AArch64, accesses to the following registers are trapped to EL2 and reported using EC syndrome value 0x14: TTBR0_EL1. TTBR1_EL1. If FEAT_THE is implemented, RCWMASK_EL1, RCWSMASK_EL1. PAR_EL1. When EL2 is not implemented or not enabled in the current Security state, the Effective value of this field is 1. Otherwise, when the Effective value of SCR_EL3.HXEn is 0, the Effective value of this field is 0. 0b0 EL1 accesses to the specified registers are disabled, and trapped to EL2. 0b1 This control does not cause any instructions to be trapped. '0' AU When FEAT_D128 is implemented 17 17 17 Reserved, RES0. Otherwise PTTWI 16 16 0 Permit Translation Table Walk Incoherence. Permits RCWS instructions to generate writes that have the Reduced Coherence property. The Effective value of this field is 1 when any of the following are true: EL2 is not implemented or not enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. The Effective value of this field is 0 when all of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}. The Effective value of SCR_EL3.HXEn is 0. This field is permitted to be cached in TLB. This field is permitted to be implemented as a read-only field with a fixed value of 0. 0b0 Write accesses generated by RCWS at EL1 and EL0 do not have the Reduced Coherence property. 0b1 Write accesses generated by RCWS at EL1 and EL0 have the Reduced Coherence property, if enabled by TCR2_EL1.PTTWI. '0' AU When FEAT_THE is implemented 16 16 16 Reserved, RES0. Otherwise SCTLR2En 15 15 0 SCTLR2_EL1 Enable. In AArch64 state, accesses to SCTLR2_EL1 are trapped to EL2 and reported using EC syndrome value 0x18. When EL2 is not implemented or not enabled in the current Security state, the Effective value of this field is 1. Otherwise, when the Effective value of SCR_EL3.HXEn is 0, the Effective value of this field is 0. 0b0 Accesses to SCTLR2_EL1 at EL1 are trapped to EL2, unless the access generates a higher priority exception. The value in SCTLR2_EL1 is treated as 0. 0b1 This control does not cause any instructions to be trapped. '0' AU When FEAT_SCTLR2 is implemented 15 15 15 Reserved, RES0. Otherwise TCR2En 14 14 0 TCR2_EL1 Enable. In AArch64 state, accesses to TCR2_EL1 are trapped to EL2 and reported using EC syndrome value 0x18. When EL2 is not implemented or not enabled in the current Security state, the Effective value of this field is 1. Otherwise, when the Effective value of SCR_EL3.HXEn is 0, the Effective value of this field is 0. 0b0 Accesses to TCR2_EL1 at EL1 are trapped to EL2, unless the access generates a higher priority exception. The value in TCR2_EL1 is treated as 0. 0b1 This control does not cause any instructions to be trapped. '0' AU When FEAT_TCR2 is implemented 14 14 14 Reserved, RES0. Otherwise 13 12 13:12 Reserved, RES0. MSCEn 11 11 0 Memory Set and Memory Copy instructions Enable. Enables execution of the CPY*, SETG*, SETP*, SETM*, and SETE* instructions at EL1 or EL0. The Effective value of this field is 1 when any of the following are true: EL2 is not implemented or not enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. The Effective value of this field is 0 when all of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}. The Effective value of SCR_EL3.HXEn is 0. 0b0 Execution of the Memory Copy and Memory Set instructions is UNDEFINED at EL1 or EL0. 0b1 This control does not cause any instructions to be UNDEFINED. '0' AU When FEAT_MOPS is implemented 11 11 11 Reserved, RES0. Otherwise MCE2 10 10 0 Controls Memory Copy and Memory Set exceptions generated as part of attempting to execute the Memory Copy and Memory Set instructions from EL1. The Effective value of this field is 0 when any of the following are true: EL2 is not implemented or not enabled in the current Security state. The Effective value of SCR_EL3.HXEn is 0. 0b0 Memory Copy and Memory Set exceptions generated from EL1 are taken to EL1. 0b1 Memory Copy and Memory Set exceptions generated from EL1 are taken to EL2. '0' AU When FEAT_MOPS is implemented 10 10 10 Reserved, RES0. Otherwise CMOW 9 9 0 Controls the required permissions for the following cache maintenance instructions executed at EL1 or EL0: Any DC instruction that operates by VA and performs a clean and invalidate operation. Any IC instruction that operates by VA. For more information, see: Stage 2 permissions. Implications of enabling the dirty state management mechanism. The Effective value of this field is 0 when any of the following are true: The Effective value of SCR_EL3.HXEn is 0. The Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. EL2 is not implemented or not enabled in the current Security state. This field is permitted to be cached in a TLB. 0b0 This control does not cause any instructions to generate a stage 2 Permission fault. 0b1 For these instructions, when executed at EL1 or EL0, the absence of stage 2 write permission generates a stage 2 permission fault. '0' AU When FEAT_CMOW is implemented 9 9 9 Reserved, RES0. Otherwise VFNMI 8 8 0 Virtual FIQ Interrupt with Superpriority. Enables signaling of virtual FIQ interrupts with Superpriority. When HCR_EL2.VF is 0, this field has no effect. The Effective value of this field is 0 when any of the following are true: EL2 is not implemented or not enabled in the current Security state. The Effective value of SCR_EL3.HXEn is 0. 0b0 When HCR_EL2.VF is 1, a signaled pending virtual FIQ interrupt does not have Superpriority. 0b1 When HCR_EL2.VF is 1, a signaled pending virtual FIQ interrupt has Superpriority. '0' AU When FEAT_NMI is implemented 8 8 8 Reserved, RES0. Otherwise VINMI 7 7 0 Virtual IRQ Interrupt with Superpriority. Enables signaling of virtual IRQ interrupts with Superpriority. When HCR_EL2.VI is 0, this field has no effect. The Effective value of this field is 0 when any of the following are true: EL2 is not implemented or not enabled in the current Security state. The Effective value of SCR_EL3.HXEn is 0. 0b0 When HCR_EL2.VI is 1, a signaled pending virtual IRQ interrupt does not have Superpriority. 0b1 When HCR_EL2.VI is 1, a signaled pending virtual IRQ interrupt has Superpriority. '0' AU When FEAT_NMI is implemented 7 7 7 Reserved, RES0. Otherwise TALLINT 6 6 0 Traps the following writes at EL1 using AArch64 to EL2, when EL2 is implemented and enabled: MSR (register) writes of ALLINT. MSR (immediate) writes of ALLINT with a value of 1. The Effective value of this field is 0 when any of the following are true: EL2 is not implemented or not enabled in the current Security state. The Effective value of SCR_EL3.HXEn is 0. 0b0 This control does not cause any instructions to be trapped. 0b1 The specified MSR accesses at EL1 using AArch64 are trapped to EL2. '0' AU When FEAT_NMI is implemented 6 6 6 Reserved, RES0. Otherwise SMPME 5 5 0 Streaming Mode Priority Mapping Enable. Controls mapping of the value of SMPRI_EL1.Priority for streaming execution priority at EL0 or EL1. When SMIDR_EL1.SMPS is '0', this field is RES0. The Effective value of this field is 0 when any of the following are true: The Effective value of SCR_EL3.HXEn is 0. The Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. EL2 is not implemented or not enabled in the current Security state. 0b0 The effective priority value is taken from SMPRI_EL1.Priority. 0b1 The effective priority value is: When the current Exception level is EL2 or EL3, the value of SMPRI_EL1.Priority. When the current Exception level is EL0 or EL1, the value of the SMPRIMAP_EL2 field corresponding to the value of SMPRI_EL1.Priority. '0' AU When FEAT_SME is implemented 5 5 5 Reserved, RES0. Otherwise FGTnXS 4 4 0 Determines if the fine-grained traps in HFGITR_EL2 that apply to each of the TLBI maintenance instructions that are accessible at EL1 also apply to the corresponding TLBI maintenance instructions with the nXS qualifier. The Effective value of this field is 0 when any of the following are true: EL2 is not implemented or not enabled in the current Security state. The Effective value of SCR_EL3.HXEn is 0. 0b0 The fine-grained trap in the HFGITR_EL2 that applies to a TLBI maintenance instruction at EL1 also applies to the corresponding TLBI instruction with the nXS qualifier at EL1. 0b1 The fine-grained trap in the HFGITR_EL2 that applies to a TLBI maintenance instruction at EL1 does not apply to the corresponding TLBI instruction with the nXS qualifier at EL1. '0' AU When FEAT_XS is implemented 4 4 4 Reserved, RES0. Otherwise FnXS 3 3 0 Determines the behavior of TLBI instructions affected by the XS attribute. This control field also determines whether an AArch64 DSB instruction behaves as a DSB instruction with an nXS qualifier when executed at EL0 and EL1. The Effective value of this field is 0 when any of the following are true: EL2 is not implemented or not enabled in the current Security state. The Effective value of SCR_EL3.HXEn is 0. This field is permitted to be cached in a TLB. 0b0 This control does not have any effect on the behavior of the TLBI maintenance instructions. 0b1 A TLBI maintenance instruction without the nXS qualifier executed at EL1 behaves in the same way as the corresponding TLBI maintenance instruction with the nXS qualifier. An AArch64 DSB instruction that applies to both loads and stores executed at EL1 or EL0 behaves in the same way as the corresponding DSB instruction with the nXS qualifier executed at EL1 or EL0. '0' AU When FEAT_XS is implemented 3 3 3 Reserved, RES0. Otherwise EnASR 2 2 0 When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps execution of an ST64BV instruction at EL0 or EL1 to EL2. A trap of an ST64BV instruction is reported using EC syndrome value 0x0A, with an ISS code of 0x0000000. The Effective value of this field is 1 when any of the following are true: EL2 is not implemented or not enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. The Effective value of this field is 0 when all of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}. The Effective value of SCR_EL3.HXEn is 0. 0b0 Execution of an ST64BV instruction at EL0 is trapped to EL2 if the execution is not trapped by SCTLR_EL1.EnASR. Execution of an ST64BV instruction at EL1 is trapped to EL2. 0b1 This control does not cause any instructions to be trapped. '0' AU When FEAT_LS64_V is implemented 2 2 2 Reserved, RES0. Otherwise EnALS 1 1 0 When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps execution of an LD64B or ST64B instruction at EL0 or EL1 to EL2. A trap of an LD64B or ST64B instruction is reported using EC syndrome value 0x0A, with an ISS code of 0x0000002. The Effective value of this field is 1 when any of the following are true: EL2 is not implemented or not enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. The Effective value of this field is 0 when all of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}. The Effective value of SCR_EL3.HXEn is 0. 0b0 Execution of an LD64B or ST64B instruction at EL0 is trapped to EL2 if the execution is not trapped by SCTLR_EL1.EnALS. Execution of an LD64B or ST64B instruction at EL1 is trapped to EL2. 0b1 This control does not cause any instructions to be trapped. '0' AU When FEAT_LS64 is implemented 1 1 1 Reserved, RES0. Otherwise EnAS0 0 0 0 When the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, traps execution of an ST64BV0 instruction at EL0 or EL1 to EL2. A trap of an ST64BV0 instruction is reported using EC syndrome value 0x0A, with an ISS code of 0x0000001. The Effective value of this field is 1 when any of the following are true: EL2 is not implemented or not enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is {1, 1}. The Effective value of this field is 0 when all of the following are true: EL2 is implemented and enabled in the current Security state. The Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}. The Effective value of SCR_EL3.HXEn is 0. 0b0 Execution of an ST64BV0 instruction at EL0 is trapped to EL2 if the execution is not trapped by SCTLR_EL1.EnAS0. Execution of an ST64BV0 instruction at EL1 is trapped to EL2. 0b1 This control does not cause any instructions to be trapped. '0' AU When FEAT_LS64_ACCDATA is implemented 0 0 0 Reserved, RES0. Otherwise MRS <Xt>, HCRX_EL2 if !(IsFeatureImplemented(FEAT_HCX) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x0A0); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().HXEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().HXEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = HCRX_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = HCRX_EL2(); end; MSR HCRX_EL2, <Xt> if !(IsFeatureImplemented(FEAT_HCX) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x0A0) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().HXEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().HXEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else HCRX_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then HCRX_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel