HDFGRTR_EL2 Hypervisor Debug Fine-Grained Read Trap Register when FEAT_FGT is implemented and FEAT_AA64 is implemented EL2 Provides controls for traps of MRS and MRC reads of debug, trace, PMU, and Statistical Profiling System registers. Unknown If EL2 is not implemented, this register is RES0 from EL3. HDFGRTR_EL2 is a 64-bit register. PMBIDR_EL1 63 63 0 Trap MRS reads of PMBIDR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of PMBIDR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of PMBIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_SPE is implemented 63 63 63 Reserved, RES0. Otherwise nPMSNEVFR_EL1 62 62 0 Trap MRS reads of PMSNEVFR_EL1 at EL1 using AArch64 to EL2. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of PMSNEVFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of PMSNEVFR_EL1 are not trapped by this mechanism. '0' AU When FEAT_SPE_FnE is implemented 62 62 62 Reserved, RES0. Otherwise nBRBDATA 61 61 0 Trap MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2: BRBINF<n>_EL1. BRBINFINJ_EL1. BRBSRC<n>_EL1. BRBSRCINJ_EL1. BRBTGT<n>_EL1. BRBTGTINJ_EL1. BRBTS_EL1. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of the specified System registers are not trapped by this mechanism. '0' AU When FEAT_BRBE is implemented 61 61 61 Reserved, RES0. Otherwise nBRBCTL 60 60 0 Trap MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2: BRBCR_EL1. BRBFCR_EL1. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of the specified System registers are not trapped by this mechanism. '0' AU When FEAT_BRBE is implemented 60 60 60 Reserved, RES0. Otherwise nBRBIDR 59 59 0 Trap MRS reads of BRBIDR0_EL1 at EL1 using AArch64 to EL2. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of BRBIDR0_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of BRBIDR0_EL1 are not trapped by this mechanism. '0' AU When FEAT_BRBE is implemented 59 59 59 Reserved, RES0. Otherwise PMCEIDn_EL0 58 58 0 Trap MRS reads of PMCEID<n>_EL0 at EL1 and EL0 using AArch64 and MRC reads of PMCEID<n> at EL0 using AArch32 when EL1 is using AArch64 to EL2. 0b0 MRS reads of PMCEID<n>_EL0 at EL1 and EL0 using AArch64 and MRC reads of PMCEID<n> at EL0 using AArch32 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the read generates a higher priority exception: MRS reads of PMCEID<n>_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRC reads of PMCEID<n> at EL0 using AArch32 when EL1 is using AArch64 are trapped to EL2 and reported with EC syndrome value 0x03. '0' AU When FEAT_PMUv3 is implemented 58 58 58 Reserved, RES0. Otherwise PMUSERENR_EL0 57 57 0 Trap MRS reads of PMUSERENR_EL0 at EL1 and EL0 using AArch64 and MRC reads of PMUSERENR at EL0 using AArch32 when EL1 is using AArch64 to EL2. 0b0 MRS reads of PMUSERENR_EL0 at EL1 and EL0 using AArch64 and MRC reads of PMUSERENR at EL0 using AArch32 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the read generates a higher priority exception: MRS reads of PMUSERENR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRC reads of PMUSERENR at EL0 using AArch32 when EL1 is using AArch64 are trapped to EL2 and reported with EC syndrome value 0x03. '0' AU When FEAT_PMUv3 is implemented 57 57 57 Reserved, RES0. Otherwise TRBTRG_EL1 56 56 0 Trap MRS reads of TRBTRG_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of TRBTRG_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRBTRG_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_TRBE is implemented 56 56 56 Reserved, RES0. Otherwise TRBSR_EL1 55 55 0 Trap MRS reads of TRBSR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of TRBSR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRBSR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_TRBE is implemented 55 55 55 Reserved, RES0. Otherwise TRBPTR_EL1 54 54 0 Trap MRS reads of TRBPTR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of TRBPTR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRBPTR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_TRBE is implemented 54 54 54 Reserved, RES0. Otherwise TRBMAR_EL1 53 53 0 Trap MRS reads of TRBMAR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of TRBMAR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRBMAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_TRBE is implemented 53 53 53 Reserved, RES0. Otherwise TRBLIMITR_EL1 52 52 0 Trap MRS reads of TRBLIMITR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of TRBLIMITR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRBLIMITR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_TRBE is implemented 52 52 52 Reserved, RES0. Otherwise TRBIDR_EL1 51 51 0 Trap MRS reads of TRBIDR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of TRBIDR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRBIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_TRBE is implemented 51 51 51 Reserved, RES0. Otherwise TRBBASER_EL1 50 50 0 Trap MRS reads of TRBBASER_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of TRBBASER_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRBBASER_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_TRBE is implemented 50 50 50 Reserved, RES0. Otherwise 49 49 49 Reserved, RES0. TRCVICTLR 48 48 0 In an Armv9 implementation, trap MRS reads of TRCVICTLR at EL1 using AArch64 to EL2. In an Armv8 implementation, trap MRS reads of ETM TRCVICTLR at EL1 using AArch64 to EL2. 0b0 MRS reads of TRCVICTLR are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRCVICTLR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_ETE is implemented or (FEAT_ETMv4 is implemented and System register access to the trace unit registers is implemented) 48 48 48 Reserved, RES0. Otherwise TRCSTATR 47 47 0 In an Armv9 implementation, trap MRS reads of TRCSTATR at EL1 using AArch64 to EL2. In an Armv8 implementation, trap MRS reads of ETM TRCSTATR at EL1 using AArch64 to EL2. 0b0 MRS reads of TRCSTATR are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRCSTATR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_ETE is implemented or (FEAT_ETMv4 is implemented and System register access to the trace unit registers is implemented) 47 47 47 Reserved, RES0. Otherwise TRCSSCSRn 46 46 0 In an Armv9 implementation, trap MRS reads of TRCSSCSR<n> at EL1 using AArch64 to EL2. In an Armv8 implementation, trap MRS reads of ETM TRCSSCSR<n> at EL1 using AArch64 to EL2. If Single-shot Comparator n is not implementented, a read of TRCSSCSR<n> is UNDEFINED. 0b0 MRS reads of TRCSSCSR<n> are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRCSSCSR<n> at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_ETE is implemented or (FEAT_ETMv4 is implemented, TRCSSCSR<n> are implemented, and System register access to the trace unit registers is implemented) 46 46 46 Reserved, RES0. Otherwise TRCSEQSTR 45 45 0 In an Armv9 implementation, trap MRS reads of TRCSEQSTR at EL1 using AArch64 to EL2. In an Armv8 implementation, trap MRS reads of ETM TRCSEQSTR at EL1 using AArch64 to EL2. 0b0 MRS reads of TRCSEQSTR are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRCSEQSTR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_ETE is implemented or (FEAT_ETMv4 is implemented, TRCSEQSTR is implemented, and System register access to the trace unit registers is implemented) 45 45 45 Reserved, RES0. Otherwise TRCPRGCTLR 44 44 0 In an Armv9 implementation, trap MRS reads of TRCPRGCTLR at EL1 using AArch64 to EL2. In an Armv8 implementation, trap MRS reads of ETM TRCPRGCTLR at EL1 using AArch64 to EL2. 0b0 MRS reads of TRCPRGCTLR are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRCPRGCTLR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_ETE is implemented or (FEAT_ETMv4 is implemented and System register access to the trace unit registers is implemented) 44 44 44 Reserved, RES0. Otherwise TRCOSLSR 43 43 0 In an Armv9 implementation, trap MRS reads of TRCOSLSR at EL1 using AArch64 to EL2. In an Armv8 implementation, trap MRS reads of ETM TRCOSLSR at EL1 using AArch64 to EL2. 0b0 MRS reads of TRCOSLSR are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRCOSLSR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_ETE is implemented or (FEAT_ETMv4 is implemented and System register access to the trace unit registers is implemented) 43 43 43 Reserved, RES0. Otherwise 42 42 42 Reserved, RES0. TRCIMSPECn 41 41 0 In an Armv9 implementation, trap MRS reads of TRCIMSPEC<n> at EL1 using AArch64 to EL2. In an Armv8 implementation, trap MRS reads of ETM TRCIMSPEC<n> at EL1 using AArch64 to EL2. TRCIMSPEC<1-7> are optional. If TRCIMSPEC<n> is not implemented, a read of TRCIMSPEC<n> is UNDEFINED. 0b0 MRS reads of TRCIMSPEC<n> are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRCIMSPEC<n> at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_ETE is implemented or (FEAT_ETMv4 is implemented and System register access to the trace unit registers is implemented) 41 41 41 Reserved, RES0. Otherwise TRCID 40 40 0 Trap MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2: In an Armv9 implementation: TRCDEVARCH. TRCDEVID. All of the TRCIDR<n> registers. In an Armv8 implementation: ETM TRCDEVARCH. ETM TRCDEVID. All of the ETM TRCIDR<n> registers. 0b0 MRS reads of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_ETE is implemented or (FEAT_ETMv4 is implemented and System register access to the trace unit registers is implemented) 40 40 40 Reserved, RES0. Otherwise 39 38 39:38 Reserved, RES0. TRCCNTVRn 37 37 0 In an Armv9 implementation, trap MRS reads of TRCCNTVR<n> at EL1 using AArch64 to EL2. In an Armv8 implementation, trap MRS reads of ETM TRCCNTVR<n> at EL1 using AArch64 to EL2. If Counter n is not implemented, a read of TRCCNTVR<n> is UNDEFINED. 0b0 MRS reads of TRCCNTVR<n> are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRCCNTVR<n> at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_ETE is implemented or (FEAT_ETMv4 is implemented, TRCCNTVR<n> are implemented, and System register access to the trace unit registers is implemented) 37 37 37 Reserved, RES0. Otherwise TRCCLAIM 36 36 0 Trap MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2: In an Armv9 implementation: TRCCLAIMCLR and TRCCLAIMSET. In an Armv8 implementation: ETM TRCCLAIMCLR and ETM TRCCLAIMSET. 0b0 MRS reads of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_ETE is implemented or (FEAT_ETMv4 is implemented and System register access to the trace unit registers is implemented) 36 36 36 Reserved, RES0. Otherwise TRCAUXCTLR 35 35 0 In an Armv9 implementation, trap MRS reads of TRCAUXCTLR at EL1 using AArch64 to EL2. In an Armv8 implementation, trap MRS reads of ETM TRCAUXCTLR at EL1 using AArch64 to EL2. 0b0 MRS reads of TRCAUXCTLR are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRCAUXCTLR at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_ETE is implemented or (FEAT_ETMv4 is implemented and System register access to the trace unit registers is implemented) 35 35 35 Reserved, RES0. Otherwise TRCAUTHSTATUS 34 34 0 In an Armv9 implementation, trap MRS reads of TRCAUTHSTATUS at EL1 using AArch64 to EL2. In an Armv8 implementation, trap MRS reads of ETM TRCAUTHSTATUS at EL1 using AArch64 to EL2. 0b0 MRS reads of TRCAUTHSTATUS are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TRCAUTHSTATUS at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_ETE is implemented or (FEAT_ETMv4 is implemented and System register access to the trace unit registers is implemented) 34 34 34 Reserved, RES0. Otherwise TRC 33 33 0 Trap MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2: In an Armv9 implementation: TRCACATR<n>. TRCACVR<n>. TRCBBCTLR. TRCCCCTLR. TRCCIDCCTLR0. TRCCIDCCTLR1. TRCCIDCVR<n>. TRCCNTCTLR<n>. TRCCNTRLDVR<n>. TRCCONFIGR. TRCEVENTCTL0R. TRCEVENTCTL1R. TRCEXTINSELR<n>. TRCQCTLR. TRCRSCTLR<n>. TRCRSR. TRCSEQEVR<n>. TRCSEQRSTEVR. TRCSSCCR<n>. TRCSSPCICR<n>. TRCSTALLCTLR. TRCSYNCPR. TRCTRACEIDR. TRCTSCTLR. TRCVIIECTLR. TRCVIPCSSCTLR. TRCVISSCTLR. TRCVMIDCCTLR0. TRCVMIDCCTLR1. TRCVMIDCVR<n>. In an Armv8 implementation: ETM TRCACATR<n>. ETM TRCACVR<n>. ETM TRCBBCTLR. ETM TRCCCCTLR. ETM TRCCIDCCTLR0. ETM TRCCIDCCTLR1. ETM TRCCIDCVR<n>. ETM TRCCNTCTLR<n>. ETM TRCCNTRLDVR<n>. ETM TRCCONFIGR. ETM TRCEVENTCTL0R. ETM TRCEVENTCTL1R. ETM TRCEXTINSELR. ETM TRCQCTLR. ETM TRCRSCTLR<n>. ETM TRCSEQEVR<n>. ETM TRCSEQRSTEVR. ETM TRCSSCCR<n>. ETM TRCSSPCICR<n>. ETM TRCSTALLCTLR. ETM TRCSYNCPR. ETM TRCTRACEIDR. ETM TRCTSCTLR. ETM TRCVIIECTLR. ETM TRCVIPCSSCTLR. ETM TRCVISSCTLR. ETM TRCVMIDCCTLR0. ETM TRCVMIDCCTLR1. ETM TRCVMIDCVR<n>. A read of an unimplemented register is UNDEFINED. TRCEXTINSELR<n> and TRCRSR are implemented only if FEAT_ETE is implemented. TRCEXTINSELR is implemented only if FEAT_ETE is not implemented and FEAT_ETMv4 is implemented. 0b0 MRS reads of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_ETE is implemented or (FEAT_ETMv4 is implemented and System register access to the trace unit registers is implemented) 33 33 33 Reserved, RES0. Otherwise PMSLATFR_EL1 32 32 0 Trap MRS reads of PMSLATFR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of PMSLATFR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of PMSLATFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_SPE is implemented 32 32 32 Reserved, RES0. Otherwise PMSIRR_EL1 31 31 0 Trap MRS reads of PMSIRR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of PMSIRR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of PMSIRR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_SPE is implemented 31 31 31 Reserved, RES0. Otherwise PMSIDR_EL1 30 30 0 Trap MRS reads of PMSIDR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of PMSIDR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of PMSIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_SPE is implemented 30 30 30 Reserved, RES0. Otherwise PMSICR_EL1 29 29 0 Trap MRS reads of PMSICR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of PMSICR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of PMSICR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_SPE is implemented 29 29 29 Reserved, RES0. Otherwise PMSFCR_EL1 28 28 0 Trap MRS reads of PMSFCR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of PMSFCR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of PMSFCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_SPE is implemented 28 28 28 Reserved, RES0. Otherwise PMSEVFR_EL1 27 27 0 Trap MRS reads of PMSEVFR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of PMSEVFR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of PMSEVFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_SPE is implemented 27 27 27 Reserved, RES0. Otherwise PMSCR_EL1 26 26 0 Trap MRS reads of PMSCR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of PMSCR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of PMSCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_SPE is implemented 26 26 26 Reserved, RES0. Otherwise PMBSR_EL1 25 25 0 Trap MRS reads of PMBSR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of PMBSR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of PMBSR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_SPE is implemented 25 25 25 Reserved, RES0. Otherwise PMBPTR_EL1 24 24 0 Trap MRS reads of PMBPTR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of PMBPTR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of PMBPTR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_SPE is implemented 24 24 24 Reserved, RES0. Otherwise PMBLIMITR_EL1 23 23 0 Trap MRS reads of PMBLIMITR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of PMBLIMITR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of PMBLIMITR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_SPE is implemented 23 23 23 Reserved, RES0. Otherwise PMMIR_EL1 22 22 0 Trap MRS reads of PMMIR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of PMMIR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of PMMIR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_PMUv3 is implemented 22 22 22 Reserved, RES0. Otherwise 21 20 21:20 Reserved, RES0. PMSELR_EL0 19 19 0 Trap MRS reads of PMSELR_EL0 at EL1 and EL0 using AArch64 and MRC reads of PMSELR at EL0 using AArch32 when EL1 is using AArch64 to EL2. 0b0 MRS reads of PMSELR_EL0 at EL1 and EL0 using AArch64 and MRC reads of PMSELR at EL0 using AArch32 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the read generates a higher priority exception: MRS reads of PMSELR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRC reads of PMSELR at EL0 using AArch32 when EL1 is using AArch64 are trapped to EL2 and reported with EC syndrome value 0x03. '0' AU When FEAT_PMUv3 is implemented 19 19 19 Reserved, RES0. Otherwise PMOVS 18 18 0 Trap MRS reads and MRC reads of any of the following System registers to EL2: At EL1 and EL0 using AArch64: PMOVSCLR_EL0 and PMOVSSET_EL0. At EL0 using AArch32 when EL1 is using AArch64: PMOVSR and PMOVSSET. 0b0 MRS reads at EL1 and EL0 using AArch64 and MRC reads at EL0 using AArch32 of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the read generates a higher priority exception: MRS reads at EL1 and EL0 using AArch64 of any of the specified AArch64 System registers are trapped to EL2 and reported with EC syndrome value 0x18. MRC reads at EL0 using AArch32 when EL1 is using AArch64 of any of the specified AArch32 System registers are trapped to EL2 and reported with EC syndrome value 0x03. '0' AU When FEAT_PMUv3 is implemented 18 18 18 Reserved, RES0. Otherwise PMINTEN 17 17 0 Trap MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2: PMINTENCLR_EL1. PMINTENSET_EL1. 0b0 MRS reads of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_PMUv3 is implemented 17 17 17 Reserved, RES0. Otherwise PMCNTEN 16 16 0 Trap MRS reads and MRC reads of any of the following System registers to EL2: At EL1 and EL0 using AArch64: PMCNTENCLR_EL0 and PMCNTENSET_EL0. At EL0 using AArch32 when EL1 is using AArch64: PMCNTENCLR and PMCNTENSET. 0b0 MRS reads at EL1 and EL0 using AArch64 and MRC reads at EL0 using AArch32 of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the read generates a higher priority exception: MRS reads at EL1 and EL0 using AArch64 of any of the specified AArch64 System registers are trapped to EL2 and reported with EC syndrome value 0x18. MRC reads at EL0 using AArch32 when EL1 is using AArch64 of any of the specified AArch32 System registers are trapped to EL2 and reported with EC syndrome value 0x03. '0' AU When FEAT_PMUv3 is implemented 16 16 16 Reserved, RES0. Otherwise PMCCNTR_EL0 15 15 0 Trap MRS reads of PMCCNTR_EL0 at EL1 and EL0 using AArch64 and MRC and MRRC reads of PMCCNTR at EL0 using AArch32 when EL1 is using AArch64 to EL2. 0b0 MRS reads of PMCCNTR_EL0 at EL1 and EL0 using AArch64 and MRC and MRRC reads of PMCCNTR at EL0 using AArch32 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the read generates a higher priority exception: MRS reads of PMCCNTR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRC reads of PMCCNTR at EL0 using AArch32 when EL1 is using AArch64 are trapped to EL2 and reported with EC syndrome value 0x03. MRRC reads of PMCCNTR at EL0 using AArch32 when EL1 is using AArch64 are trapped to EL2 and reported with EC syndrome value 0x04. '0' AU When FEAT_PMUv3 is implemented 15 15 15 Reserved, RES0. Otherwise PMCCFILTR_EL0 14 14 0 Trap MRS reads of PMCCFILTR_EL0 at EL1 and EL0 using AArch64 and MRC reads of PMCCFILTR at EL0 using AArch32 when EL1 is using AArch64 to EL2. PMCCFILTR_EL0 can also be accessed in AArch64 state using PMXEVTYPER_EL0 when PMSELR_EL0.SEL == 31, and PMCCFILTR can also be accessed in AArch32 state using PMXEVTYPER when PMSELR.SEL == 31. Setting this field to 1 has no effect on accesses to PMXEVTYPER_EL0 and PMXEVTYPER, regardless of the value of PMSELR_EL0.SEL or PMSELR.SEL. 0b0 MRS reads of PMCCFILTR_EL0 at EL1 and EL0 using AArch64 and MRC reads of PMCCFILTR at EL0 using AArch32 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the read generates a higher priority exception: MRS reads of PMCCFILTR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRC reads of PMCCFILTR at EL0 using AArch32 when EL1 is using AArch64 are trapped to EL2 and reported with EC syndrome value 0x03. '0' AU When FEAT_PMUv3 is implemented 14 14 14 Reserved, RES0. Otherwise PMEVTYPERn_EL0 13 13 0 Trap MRS reads and MRC reads of any of the following System registers to EL2: At EL1 and EL0 using AArch64: PMEVTYPER<n>_EL0 and PMXEVTYPER_EL0. At EL0 using AArch32 when EL1 is using AArch64: PMEVTYPER<n> and PMXEVTYPER. Regardless of the value of this field, for each value n: If event counter n is not implemented, the following accesses are UNDEFINED: In AArch64 state, a read of PMEVTYPER<n>_EL0, or, if n is not 31, a read of PMXEVTYPER_EL0 when PMSELR_EL0.SEL == n. In AArch32 state, a read of PMEVTYPER<n>, or, if n is not 31, a read of PMXEVTYPER when PMSELR.SEL == n. If event counter n is implemented, n is greater-than-or-equal-to MDCR_EL2.HPMN, and EL2 is implemented and enabled in the current Security state, the following generate a Trap exception to EL2 from EL0 or EL1: In AArch64 state, a read of PMEVTYPER<n>_EL0, or a read of PMXEVTYPER_EL0 when PMSELR_EL0.SEL == n, reported with EC syndrome value 0x18. In AArch32 state, a read of PMEVTYPER<n>, or a read of PMXEVTYPER when PMSELR.SEL == n, reported with EC syndrome value 0x03. See also HDFGRTR_EL2.PMCCFILTR_EL0. 0b0 MRS reads at EL1 and EL0 using AArch64 and MRC reads at EL0 using AArch32 of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the read generates a higher priority exception: MRS reads at EL1 and EL0 using AArch64 of any of the specified AArch64 System registers are trapped to EL2 and reported with EC syndrome value 0x18. MRC reads at EL0 using AArch32 when EL1 is using AArch64 of any of the specified AArch32 System registers are trapped to EL2 and reported with EC syndrome value 0x03. '0' AU When FEAT_PMUv3 is implemented 13 13 13 Reserved, RES0. Otherwise PMEVCNTRn_EL0 12 12 0 Trap MRS reads and MRC reads of any of the following System registers to EL2: At EL1 and EL0 using AArch64: PMEVCNTR<n>_EL0 and PMXEVCNTR_EL0. At EL0 using AArch32 when EL1 is using AArch64: PMEVCNTR<n> and PMXEVCNTR. Regardless of the value of this field, for each value n: If event counter n is not implemented, the following accesses are UNDEFINED: In AArch64 state, a read of PMEVCNTR<n>_EL0, or a read of PMXEVCNTR_EL0 when PMSELR_EL0.SEL is n. In AArch32 state, a read of PMEVCNTR<n>, or a read of PMXEVCNTR when PMSELR.SEL is n. If event counter n is implemented, n is greater than or equal to MDCR_EL2.HPMN, and EL2 is implemented and enabled in the current Security state, the following generate a Trap exception to EL2 from EL0 or EL1: In AArch64 state, a read of PMEVCNTR<n>_EL0, or a read of PMXEVCNTR_EL0 when PMSELR_EL0.SEL is n, reported with EC syndrome value 0x18. In AArch32 state, a read of PMEVCNTR<n>, or a read of PMXEVCNTR when PMSELR.SEL is n, reported with EC syndrome value 0x03. 0b0 MRS reads at EL1 and EL0 using AArch64 and MRC reads at EL0 using AArch32 of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the read generates a higher priority exception: MRS reads at EL1 and EL0 using AArch64 of any of the specified AArch64 System registers are trapped to EL2 and reported with EC syndrome value 0x18. MRC reads at EL0 using AArch32 when EL1 is using AArch64 of any of the specified AArch32 System registers are trapped to EL2 and reported with EC syndrome value 0x03. '0' AU When FEAT_PMUv3 is implemented 12 12 12 Reserved, RES0. Otherwise OSDLR_EL1 11 11 0 Trap MRS reads of OSDLR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of OSDLR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of OSDLR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_DoubleLock is implemented 11 11 11 Reserved, RES0. Otherwise OSECCR_EL1 10 10 10 Trap MRS reads of OSECCR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of OSECCR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of OSECCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU OSLSR_EL1 9 9 9 Trap MRS reads of OSLSR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of OSLSR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of OSLSR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU 8 8 8 Reserved, RES0. DBGPRCR_EL1 7 7 7 Trap MRS reads of DBGPRCR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of DBGPRCR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of DBGPRCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU DBGAUTHSTATUS_EL1 6 6 6 Trap MRS reads of DBGAUTHSTATUS_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of DBGAUTHSTATUS_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of DBGAUTHSTATUS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU DBGCLAIM 5 5 5 Trap MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2: DBGCLAIMCLR_EL1. DBGCLAIMSET_EL1. 0b0 MRS reads of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU MDSCR_EL1 4 4 4 Trap MRS reads of MDSCR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of MDSCR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of MDSCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU DBGWVRn_EL1 3 3 3 Trap MRS reads of DBGWVR<n>_EL1 at EL1 using AArch64 to EL2. If watchpoint n is not implemented, a read of DBGWVR<n>_EL1 is UNDEFINED. 0b0 MRS reads of DBGWVR<n>_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of DBGWVR<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU DBGWCRn_EL1 2 2 2 Trap MRS reads of DBGWCR<n>_EL1 at EL1 using AArch64 to EL2. If watchpoint n is not implemented, a read of DBGWCR<n>_EL1 is UNDEFINED. 0b0 MRS reads of DBGWCR<n>_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of DBGWCR<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU DBGBVRn_EL1 1 1 1 Trap MRS reads of DBGBVR<n>_EL1 at EL1 using AArch64 to EL2. If breakpoint n is not implemented, a read of DBGBVR<n>_EL1 is UNDEFINED. 0b0 MRS reads of DBGBVR<n>_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of DBGBVR<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU DBGBCRn_EL1 0 0 0 Trap MRS reads of DBGBCR<n>_EL1 at EL1 using AArch64 to EL2. If breakpoint n is not implemented, a read of DBGBCR<n>_EL1 is UNDEFINED. 0b0 MRS reads of DBGBCR<n>_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of DBGBCR<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU MRS <Xt>, HDFGRTR_EL2 if !(IsFeatureImplemented(FEAT_FGT) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x1D0); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = HDFGRTR_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = HDFGRTR_EL2(); end; MSR HDFGRTR_EL2, <Xt> if !(IsFeatureImplemented(FEAT_FGT) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x1D0) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else HDFGRTR_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then HDFGRTR_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel