HDFGWTR2_EL2 Hypervisor Debug Fine-Grained Write Trap Register 2 when FEAT_FGT2 is implemented and FEAT_AA64 is implemented Provides controls for traps of MSR and MCR writes of debug, trace, PMU, and Statistical Profiling System registers. Unknown If EL2 is not implemented, this register is RES0 from EL3. HDFGWTR2_EL2 is a 64-bit register. 63 25 63:25 Reserved, RES0. nPMBMAR_EL1 24 24 0 Trap MSR writes of PMBMAR_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MSR writes of PMBMAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of PMBMAR_EL1 are not trapped by this mechanism. '0' AU When FEAT_SPE_nVM is implemented 24 24 24 Reserved, RES0. Otherwise nMDSTEPOP_EL1 23 23 0 Trap MSR writes of MDSTEPOP_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MSR writes of MDSTEPOP_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of MDSTEPOP_EL1 are not trapped by this mechanism. '0' AU When FEAT_STEP2 is implemented 23 23 23 Reserved, RES0. Otherwise nTRBMPAM_EL1 22 22 0 Trap MSR writes of TRBMPAM_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MSR writes of TRBMPAM_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of TRBMPAM_EL1 are not trapped by this mechanism. '0' AU When FEAT_TRBE_MPAM is implemented 22 22 22 Reserved, RES0. Otherwise nPMZR_EL0 21 21 0 Trap MSR writes of PMZR_EL0 at EL1 and EL0 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, and the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, then MSR writes of PMZR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of PMZR_EL0 are not trapped by this mechanism. '0' AU When FEAT_PMUv3p9 is implemented 21 21 21 Reserved, RES0. Otherwise nTRCITECR_EL1 20 20 0 Trap MSR writes of TRCITECR_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MSR writes of TRCITECR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of TRCITECR_EL1 are not trapped by this mechanism. '0' AU When FEAT_ITE is implemented 20 20 20 Reserved, RES0. Otherwise nPMSDSFR_EL1 19 19 0 Trap MSR writes of PMSDSFR_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MSR writes of PMSDSFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of PMSDSFR_EL1 are not trapped by this mechanism. '0' AU When FEAT_SPE_FDS is implemented 19 19 19 Reserved, RES0. Otherwise 18 17 18:17 Reserved, RES0. nSPMSCR_EL1 16 16 0 Trap MSR writes of SPMSCR_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MSR writes of SPMSCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of SPMSCR_EL1 are not trapped by this mechanism. '0' AU When FEAT_SPMU is implemented 16 16 16 Reserved, RES0. Otherwise nSPMACCESSR_EL1 15 15 0 Trap MSR writes of SPMACCESSR_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MSR writes of SPMACCESSR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of SPMACCESSR_EL1 are not trapped by this mechanism. '0' AU When FEAT_SPMU is implemented 15 15 15 Reserved, RES0. Otherwise nSPMCR_EL0 14 14 0 Trap MSR writes of SPMCR_EL0 at EL1 and EL0 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, and the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, then MSR writes of SPMCR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of SPMCR_EL0 are not trapped by this mechanism. '0' AU When FEAT_SPMU is implemented 14 14 14 Reserved, RES0. Otherwise nSPMOVS 13 13 0 Trap MSR writes at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2: SPMOVSCLR_EL0. SPMOVSSET_EL0. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, and the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, then MSR writes at EL1 and EL0 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of the specified System registers are not trapped by this mechanism. '0' AU When FEAT_SPMU is implemented 13 13 13 Reserved, RES0. Otherwise nSPMINTEN 12 12 0 Trap MSR writes at EL1 using AArch64 of any of the following AArch64 System registers to EL2: SPMINTENCLR_EL1. SPMINTENSET_EL1. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MSR writes at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of the specified System registers are not trapped by this mechanism. '0' AU When FEAT_SPMU is implemented 12 12 12 Reserved, RES0. Otherwise nSPMCNTEN 11 11 0 Trap MSR writes at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2: SPMCNTENCLR_EL0. SPMCNTENSET_EL0. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, and the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, then MSR writes at EL1 and EL0 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of the specified System registers are not trapped by this mechanism. '0' AU When FEAT_SPMU is implemented 11 11 11 Reserved, RES0. Otherwise nSPMSELR_EL0 10 10 0 Trap MSR writes of SPMSELR_EL0 at EL1 and EL0 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, and the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, then MSR writes of SPMSELR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of SPMSELR_EL0 are not trapped by this mechanism. '0' AU When FEAT_SPMU is implemented 10 10 10 Reserved, RES0. Otherwise nSPMEVTYPERn_EL0 9 9 0 Trap MSR writes at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2: SPMEVTYPER<n>_EL0. SPMEVFILTR<n>_EL0. SPMEVFILT2R<n>_EL0. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, and the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, then MSR writes at EL1 and EL0 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of the specified System registers are not trapped by this mechanism. '0' AU When FEAT_SPMU is implemented 9 9 9 Reserved, RES0. Otherwise nSPMEVCNTRn_EL0 8 8 0 Trap MSR writes at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2: SPMEVCNTR<n>_EL0. SPMZR_EL0. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, and the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, then MSR writes at EL1 and EL0 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of the specified System registers are not trapped by this mechanism. '0' AU When FEAT_SPMU is implemented 8 8 8 Reserved, RES0. Otherwise nPMSSCR_EL1 7 7 0 Trap MSR writes of PMSSCR_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MSR writes of PMSSCR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of PMSSCR_EL1 are not trapped by this mechanism. '0' AU When FEAT_PMUv3_SS is implemented 7 7 7 Reserved, RES0. Otherwise 6 6 6 Reserved, RES0. nMDSELR_EL1 5 5 0 Trap MSR writes of MDSELR_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. It is IMPLEMENTATION DEFINED whether this field is implemented or is RES0 when 16 or fewer breakpoints are implemented, 16 or fewer watchpoints are implemented, and MDSELR_EL1 is implemented as RAZ/WI. 0b0 If EL2 is implemented and enabled in the current Security state, then MSR writes of MDSELR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of MDSELR_EL1 are not trapped by this mechanism. '0' AU When FEAT_Debugv8p9 is implemented 5 5 5 Reserved, RES0. Otherwise nPMUACR_EL1 4 4 0 Trap MSR writes of PMUACR_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MSR writes of PMUACR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of PMUACR_EL1 are not trapped by this mechanism. '0' AU When FEAT_PMUv3p9 is implemented 4 4 4 Reserved, RES0. Otherwise nPMICFILTR_EL0 3 3 0 Trap MSR writes of PMICFILTR_EL0 at EL1 and EL0 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, and the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, then: MSR writes of PMICFILTR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. PMCNTENCLR_EL0.F0, PMCNTENSET_EL0.F0, PMOVSCLR_EL0.F0, and PMOVSSET_EL0.F0 ignore writes at EL1 and EL0. PMINTENCLR_EL1.F0 and PMINTENSET_EL1.F0 ignore writes at EL1. 0b1 MSR writes of PMICFILTR_EL0 are not trapped by this mechanism. '0' AU When FEAT_PMUv3_ICNTR is implemented 3 3 3 Reserved, RES0. Otherwise nPMICNTR_EL0 2 2 0 Trap MSR writes of PMICNTR_EL0 at EL1 and EL0 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, and the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, then: MSR writes of PMICNTR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. PMZR_EL0.F0 ignores writes at EL1 and EL0. 0b1 MSR writes of PMICNTR_EL0 are not trapped by this mechanism. '0' AU When FEAT_PMUv3_ICNTR is implemented 2 2 2 Reserved, RES0. Otherwise 1 1 1 Reserved, RES0. nPMECR_EL1 0 0 0 Trap MSR writes of PMECR_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MSR writes of PMECR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the write generates a higher priority exception. 0b1 MSR writes of PMECR_EL1 are not trapped by this mechanism. '0' AU When FEAT_EBEP is implemented or FEAT_PMUv3_SS is implemented 0 0 0 Reserved, RES0. Otherwise MRS <Xt>, HDFGWTR2_EL2 if !(IsFeatureImplemented(FEAT_FGT2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x1B0); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn2 == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = HDFGWTR2_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = HDFGWTR2_EL2(); end; MSR HDFGWTR2_EL2, <Xt> if !(IsFeatureImplemented(FEAT_FGT2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x1B0) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn2 == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else HDFGWTR2_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then HDFGWTR2_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel