HFGITR2_EL2 Hypervisor Fine-Grained Instruction Trap Register 2 when FEAT_FGT2 is implemented and FEAT_AA64 is implemented Provides instruction trap controls. Virt If EL2 is not implemented, this register is RES0 from EL3. HFGITR2_EL2 is a 64-bit register. 63 2 63:2 Reserved, RES0. nDCCIVAPS 1 1 0 Trap execution of any of the following AArch64 instructions at EL1 to EL2: DC CIVAPS. DC CIGDVAPS, if FEAT_MTE2 is implemented. If the Point of Physical Storage is before any level of data cache, it is IMPLEMENTATION DEFINED whether the execution of the affected instruction is trapped when the value of this control is 1. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then execution at EL1 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. 0b1 Execution of the specified instructions is not trapped by this mechanism. '0' AU When FEAT_PoPS is implemented 1 1 1 Reserved, RES0. Otherwise TSBCSYNC 0 0 0 Trap execution of TSB CSYNC at EL1 and EL0 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 Execution of TSB CSYNC is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, then execution of TSB CSYNC at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x0A, unless the instruction generates a higher priority exception. '0' AU When FEAT_TRBEv1p1 is implemented 0 0 0 Reserved, RES0. Otherwise MRS <Xt>, HFGITR2_EL2 if !(IsFeatureImplemented(FEAT_FGT2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x310); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn2 == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = HFGITR2_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = HFGITR2_EL2(); end; MSR HFGITR2_EL2, <Xt> if !(IsFeatureImplemented(FEAT_FGT2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x310) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn2 == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else HFGITR2_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then HFGITR2_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel