HFGITR_EL2 Hypervisor Fine-Grained Instruction Trap Register when FEAT_FGT is implemented and FEAT_AA64 is implemented EL2 Provides instruction trap controls. Unknown If EL2 is not implemented, this register is RES0 from EL3. HFGITR_EL2 is a 64-bit register. PSBCSYNC 63 63 0 Trap execution of PSB CSYNC at EL1 and EL0 using AArch64 to EL2. 0b0 Execution of PSB CSYNC is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of PSB CSYNC at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x0A, unless the instruction generates a higher priority exception. '0' AU When FEAT_SPEv1p5 is implemented 63 63 63 Reserved, RES0. Otherwise ATS1E1A 62 62 0 Trap execution of AT S1E1A at EL1 using AArch64 to EL2. 0b0 Execution of AT S1E1A is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of AT S1E1A at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_ATS1A is implemented 62 62 62 Reserved, RES0. Otherwise 61 61 61 Reserved, RES0. COSPRCTX 60 60 0 Trap execution of COSP RCTX at EL1 and EL0 using AArch64 and execution of COSPRCTX at EL0 using AArch32 when EL1 is using AArch64 to EL2. 0b0 Execution of COSP RCTX at EL1 and EL0 using AArch64 and execution of COSPRCTX at EL0 using AArch32 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the instruction generates a higher priority exception: Execution of COSP RCTX at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18. Execution of COSPRCTX at EL0 using AArch32 when EL1 is using AArch64 is trapped to EL2 and reported with EC syndrome value 0x03. '0' AU When FEAT_SPECRES2 is implemented 60 60 60 Reserved, RES0. Otherwise nGCSEPP 59 59 0 Trap execution of any of the following AArch64 instructions at EL1 to EL2: GCSPUSHX. GCSPOPCX. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution at EL1 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. 0b1 Execution of the specified instructions is not trapped by this mechanism. '0' AU When FEAT_GCS is implemented 59 59 59 Reserved, RES0. Otherwise nGCSSTR_EL1 58 58 0 Trap execution of any of the following AArch64 instructions at EL1 to EL2: GCSSTR. GCSSTTR when PSTATE.UAO is 1. GCSSTTR when the Effective value of HCR_EL2.{NV, NV1} is {1, 1}. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution at EL1 using AArch64 of any of the specified instructions generates a GCS exception with EC syndrome value 0x2D, unless the instruction generates a higher priority exception. 0b1 Execution of the specified instructions is not trapped by this mechanism. '0' AU When FEAT_GCS is implemented 58 58 58 Reserved, RES0. Otherwise nGCSPUSHM_EL1 57 57 0 Trap execution of GCSPUSHM at EL1 using AArch64 to EL2. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of GCSPUSHM at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. 0b1 Execution of GCSPUSHM is not trapped by this mechanism. '0' AU When FEAT_GCS is implemented 57 57 57 Reserved, RES0. Otherwise nBRBIALL 56 56 0 Trap execution of BRB IALL at EL1 using AArch64 to EL2. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of BRB IALL at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. 0b1 Execution of BRB IALL is not trapped by this mechanism. '0' AU When FEAT_BRBE is implemented 56 56 56 Reserved, RES0. Otherwise nBRBINJ 55 55 0 Trap execution of BRB INJ at EL1 using AArch64 to EL2. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of BRB INJ at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. 0b1 Execution of BRB INJ is not trapped by this mechanism. '0' AU When FEAT_BRBE is implemented 55 55 55 Reserved, RES0. Otherwise DCCVAC 54 54 54 Trap execution of any of the following AArch64 instructions at EL1 and EL0 to EL2: DC CVAC. DC CGVAC, if FEAT_MTE is implemented. DC CGDVAC, if FEAT_MTE is implemented. DC CVAOC, if FEAT_OCCMO is implemented. DC CGDVAOC, if FEAT_OCCMO is implemented. 0b0 Execution of the specified instructions is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution at EL1 and EL0 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU SVC_EL1 53 53 53 Trap execution of SVC at EL1 using AArch64 to EL2. 0b0 Execution of SVC is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of SVC at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x15, unless the instruction generates a higher priority exception. '0' AU SVC_EL0 52 52 52 Trap execution of SVC at EL0 using AArch64 and execution of SVC at EL0 using AArch32 when EL1 is using AArch64 to EL2. 0b0 Execution of SVC at EL0 using AArch64 and execution of SVC at EL0 using AArch32 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the instruction generates a higher priority exception: Execution of SVC at EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x15. Execution of SVC at EL0 using AArch32 when EL1 is using AArch64 is trapped to EL2 and reported with EC syndrome value 0x11. '0' AU ERET 51 51 51 Trap execution of any of the following AArch64 instructions at EL1 to EL2: ERET. ERETAA, if FEAT_PAuth is implemented. ERETAB, if FEAT_PAuth is implemented. If EL2 is implemented and enabled in the current Security state, HCR_EL2.API == 0, and this field enables a fine-grained trap on the instruction, then execution at EL1 using AArch64 of ERETAA or ERETAB instructions is trapped to EL2 and reported with EC syndrome value 0x1A with its associated ISS field, as the fine-grained trap has higher priority than the trap enabled by HCR_EL2.API == 0. 0b0 Execution of the specified instructions is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution at EL1 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x1A, unless the instruction generates a higher priority exception. '0' AU CPPRCTX 50 50 0 Trap execution of CPP RCTX at EL1 and EL0 using AArch64 and execution of CPPRCTX at EL0 using AArch32 when EL1 is using AArch64 to EL2. 0b0 Execution of CPP RCTX at EL1 and EL0 using AArch64 and execution of CPPRCTX at EL0 using AArch32 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the instruction generates a higher priority exception: Execution of CPP RCTX at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18. Execution of CPPRCTX at EL0 using AArch32 when EL1 is using AArch64 is trapped to EL2 and reported with EC syndrome value 0x03. '0' AU When FEAT_SPECRES is implemented 50 50 50 Reserved, RES0. Otherwise DVPRCTX 49 49 0 Trap execution of DVP RCTX at EL1 and EL0 using AArch64 and execution of DVPRCTX at EL0 using AArch32 when EL1 is using AArch64 to EL2. 0b0 Execution of DVP RCTX at EL1 and EL0 using AArch64 and execution of DVPRCTX at EL0 using AArch32 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the instruction generates a higher priority exception: Execution of DVP RCTX at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18. Execution of DVPRCTX at EL0 using AArch32 when EL1 is using AArch64 is trapped to EL2 and reported with EC syndrome value 0x03. '0' AU When FEAT_SPECRES is implemented 49 49 49 Reserved, RES0. Otherwise CFPRCTX 48 48 0 Trap execution of CFP RCTX at EL1 and EL0 using AArch64 and execution of CFPRCTX at EL0 using AArch32 when EL1 is using AArch64 to EL2. 0b0 Execution of CFP RCTX at EL1 and EL0 using AArch64 and execution of CFPRCTX at EL0 using AArch32 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the instruction generates a higher priority exception: Execution of CFP RCTX at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18. Execution of CFPRCTX at EL0 using AArch32 when EL1 is using AArch64 is trapped to EL2 and reported with EC syndrome value 0x03. '0' AU When FEAT_SPECRES is implemented 48 48 48 Reserved, RES0. Otherwise TLBIVAALE1 47 47 47 Trap execution of TLBI VAALE1 at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAALE1NXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAALE1. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAALE1NXS. 0b0 Execution of TLBI VAALE1 is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAALE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU TLBIVALE1 46 46 46 Trap execution of TLBI VALE1 at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VALE1NXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP VALE1. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VALE1NXS. 0b0 Execution of TLBI VALE1 is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VALE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU TLBIVAAE1 45 45 45 Trap execution of TLBI VAAE1 at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAAE1NXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAAE1. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAAE1NXS. 0b0 Execution of TLBI VAAE1 is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAAE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU TLBIASIDE1 44 44 44 Trap execution of TLBI ASIDE1 at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI ASIDE1NXS. 0b0 Execution of TLBI ASIDE1 is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI ASIDE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU TLBIVAE1 43 43 43 Trap execution of TLBI VAE1 at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAE1NXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAE1. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAE1NXS. 0b0 Execution of TLBI VAE1 is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU TLBIVMALLE1 42 42 42 Trap execution of TLBI VMALLE1 at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VMALLE1NXS. 0b0 Execution of TLBI VMALLE1 is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VMALLE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU TLBIRVAALE1 41 41 0 Trap execution of TLBI RVAALE1 at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAALE1NXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAALE1. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAALE1NXS. 0b0 Execution of TLBI RVAALE1 is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAALE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIRANGE is implemented 41 41 41 Reserved, RES0. Otherwise TLBIRVALE1 40 40 0 Trap execution of TLBI RVALE1 at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVALE1NXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVALE1. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVALE1NXS. 0b0 Execution of TLBI RVALE1 is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVALE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIRANGE is implemented 40 40 40 Reserved, RES0. Otherwise TLBIRVAAE1 39 39 0 Trap execution of TLBI RVAAE1 at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAAE1NXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAAE1. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAAE1NXS. 0b0 Execution of TLBI RVAAE1 is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAAE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIRANGE is implemented 39 39 39 Reserved, RES0. Otherwise TLBIRVAE1 38 38 0 Trap execution of TLBI RVAE1 at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAE1NXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAE1. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAE1NXS. 0b0 Execution of TLBI RVAE1 is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAE1 at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIRANGE is implemented 38 38 38 Reserved, RES0. Otherwise TLBIRVAALE1IS 37 37 0 Trap execution of TLBI RVAALE1IS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAALE1ISNXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAALE1IS. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAALE1ISNXS. 0b0 Execution of TLBI RVAALE1IS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAALE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIRANGE is implemented 37 37 37 Reserved, RES0. Otherwise TLBIRVALE1IS 36 36 0 Trap execution of TLBI RVALE1IS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVALE1ISNXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVALE1IS. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVALE1ISNXS. 0b0 Execution of TLBI RVALE1IS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVALE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIRANGE is implemented 36 36 36 Reserved, RES0. Otherwise TLBIRVAAE1IS 35 35 0 Trap execution of TLBI RVAAE1IS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAAE1ISNXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAAE1IS. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAAE1ISNXS. 0b0 Execution of TLBI RVAAE1IS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAAE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIRANGE is implemented 35 35 35 Reserved, RES0. Otherwise TLBIRVAE1IS 34 34 0 Trap execution of TLBI RVAE1IS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAE1ISNXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAE1IS. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAE1ISNXS. 0b0 Execution of TLBI RVAE1IS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIRANGE is implemented 34 34 34 Reserved, RES0. Otherwise TLBIVAALE1IS 33 33 33 Trap execution of TLBI VAALE1IS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAALE1ISNXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAALE1IS. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAALE1ISNXS. 0b0 Execution of TLBI VAALE1IS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAALE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU TLBIVALE1IS 32 32 32 Trap execution of TLBI VALE1IS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VALE1ISNXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP VALE1IS. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VALE1ISNXS. 0b0 Execution of TLBI VALE1IS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VALE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU TLBIVAAE1IS 31 31 31 Trap execution of TLBI VAAE1IS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAAE1ISNXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAAE1IS. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAAE1ISNXS. 0b0 Execution of TLBI VAAE1IS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAAE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU TLBIASIDE1IS 30 30 30 Trap execution of TLBI ASIDE1IS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI ASIDE1ISNXS. 0b0 Execution of TLBI ASIDE1IS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI ASIDE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU TLBIVAE1IS 29 29 29 Trap execution of TLBI VAE1IS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAE1ISNXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAE1IS. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAE1ISNXS. 0b0 Execution of TLBI VAE1IS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU TLBIVMALLE1IS 28 28 28 Trap execution of TLBI VMALLE1IS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VMALLE1ISNXS. 0b0 Execution of TLBI VMALLE1IS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VMALLE1IS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU TLBIRVAALE1OS 27 27 0 Trap execution of TLBI RVAALE1OS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAALE1OSNXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAALE1OS. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAALE1OSNXS. 0b0 Execution of TLBI RVAALE1OS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAALE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIRANGE is implemented and FEAT_TLBIOS is implemented 27 27 27 Reserved, RES0. Otherwise TLBIRVALE1OS 26 26 0 Trap execution of TLBI RVALE1OS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVALE1OSNXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVALE1OS. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVALE1OSNXS. 0b0 Execution of TLBI RVALE1OS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVALE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIRANGE is implemented and FEAT_TLBIOS is implemented 26 26 26 Reserved, RES0. Otherwise TLBIRVAAE1OS 25 25 0 Trap execution of TLBI RVAAE1OS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAAE1OSNXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAAE1OS. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAAE1OSNXS. 0b0 Execution of TLBI RVAAE1OS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAAE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIRANGE is implemented and FEAT_TLBIOS is implemented 25 25 25 Reserved, RES0. Otherwise TLBIRVAE1OS 24 24 0 Trap execution of TLBI RVAE1OS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI RVAE1OSNXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP RVAE1OS. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP RVAE1OSNXS. 0b0 Execution of TLBI RVAE1OS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI RVAE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIRANGE is implemented and FEAT_TLBIOS is implemented 24 24 24 Reserved, RES0. Otherwise TLBIVAALE1OS 23 23 0 Trap execution of TLBI VAALE1OS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAALE1OSNXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAALE1OS. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAALE1OSNXS. 0b0 Execution of TLBI VAALE1OS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAALE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIOS is implemented 23 23 23 Reserved, RES0. Otherwise TLBIVALE1OS 22 22 0 Trap execution of TLBI VALE1OS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VALE1OSNXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP VALE1OS. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VALE1OSNXS. 0b0 Execution of TLBI VALE1OS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VALE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIOS is implemented 22 22 22 Reserved, RES0. Otherwise TLBIVAAE1OS 21 21 0 Trap execution of TLBI VAAE1OS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAAE1OSNXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAAE1OS. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAAE1OSNXS. 0b0 Execution of TLBI VAAE1OS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAAE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIOS is implemented 21 21 21 Reserved, RES0. Otherwise TLBIASIDE1OS 20 20 0 Trap execution of TLBI ASIDE1OS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI ASIDE1OSNXS. 0b0 Execution of TLBI ASIDE1OS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI ASIDE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIOS is implemented 20 20 20 Reserved, RES0. Otherwise TLBIVAE1OS 19 19 0 Trap execution of TLBI VAE1OS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VAE1OSNXS. If FEAT_D128 is implemented, then this field also traps execution of TLBIP VAE1OS. If FEAT_XS and FEAT_D128 are implemented, then this field also traps execution of TLBIP VAE1OSNXS. 0b0 Execution of TLBI VAE1OS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VAE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIOS is implemented 19 19 19 Reserved, RES0. Otherwise TLBIVMALLE1OS 18 18 0 Trap execution of TLBI VMALLE1OS at EL1 using AArch64 to EL2. If FEAT_XS is implemented and HCRX_EL2.FGTnXS == 0, this field also traps execution of TLBI VMALLE1OSNXS. 0b0 Execution of TLBI VMALLE1OS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of TLBI VMALLE1OS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_TLBIOS is implemented 18 18 18 Reserved, RES0. Otherwise ATS1E1WP 17 17 0 Trap execution of AT S1E1WP at EL1 using AArch64 to EL2. 0b0 Execution of AT S1E1WP is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of AT S1E1WP at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_PAN2 is implemented 17 17 17 Reserved, RES0. Otherwise ATS1E1RP 16 16 0 Trap execution of AT S1E1RP at EL1 using AArch64 to EL2. 0b0 Execution of AT S1E1RP is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of AT S1E1RP at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_PAN2 is implemented 16 16 16 Reserved, RES0. Otherwise ATS1E0W 15 15 15 Trap execution of AT S1E0W at EL1 using AArch64 to EL2. 0b0 Execution of AT S1E0W is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of AT S1E0W at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU ATS1E0R 14 14 14 Trap execution of AT S1E0R at EL1 using AArch64 to EL2. 0b0 Execution of AT S1E0R is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of AT S1E0R at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU ATS1E1W 13 13 13 Trap execution of AT S1E1W at EL1 using AArch64 to EL2. 0b0 Execution of AT S1E1W is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of AT S1E1W at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU ATS1E1R 12 12 12 Trap execution of AT S1E1R at EL1 using AArch64 to EL2. 0b0 Execution of AT S1E1R is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution of AT S1E1R at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU DCZVA 11 11 11 Trap execution of any of the following AArch64 instructions at EL1 and EL0 to EL2: DC ZVA. DC GVA, if FEAT_MTE is implemented. DC GZVA, if FEAT_MTE is implemented. Unlike HCR_EL2.TDZ, this field has no effect on DCZID_EL0.DZP. 0b0 Execution of the specified instructions is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution at EL1 and EL0 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU DCCIVAC 10 10 10 Trap execution of any of the following AArch64 instructions at EL1 and EL0 to EL2: DC CIVAC. DC CIGVAC, if FEAT_MTE is implemented. DC CIGDVAC, if FEAT_MTE is implemented. DC CIVAOC, if FEAT_OCCMO is implemented. DC CIGDVAOC, if FEAT_OCCMO is implemented. 0b0 Execution of the specified instructions is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution at EL1 and EL0 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU DCCVADP 9 9 0 Trap execution of any of the following AArch64 instructions at EL1 and EL0 to EL2: DC CVADP. DC CGVADP, if FEAT_MTE is implemented. DC CGDVADP, if FEAT_MTE is implemented. 0b0 Execution of the specified instructions is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution at EL1 and EL0 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU When FEAT_DPB2 is implemented 9 9 9 Reserved, RES0. Otherwise DCCVAP 8 8 8 Trap execution of any of the following AArch64 instructions at EL1 and EL0 to EL2: DC CVAP. DC CGVAP, if FEAT_MTE is implemented. DC CGDVAP, if FEAT_MTE is implemented. 0b0 Execution of the specified instructions is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution at EL1 and EL0 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU DCCVAU 7 7 7 Trap execution of DC CVAU at EL1 and EL0 using AArch64 to EL2. 0b0 Execution of DC CVAU is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution of DC CVAU at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU DCCISW 6 6 6 Trap execution of any of the following AArch64 instructions at EL1 to EL2: DC CISW. DC CIGSW, if FEAT_MTE2 is implemented. DC CIGDSW, if FEAT_MTE2 is implemented. 0b0 Execution of the specified instructions is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution at EL1 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU DCCSW 5 5 5 Trap execution of any of the following AArch64 instructions at EL1 to EL2: DC CSW. DC CGSW, if FEAT_MTE2 is implemented. DC CGDSW, if FEAT_MTE2 is implemented. 0b0 Execution of the specified instructions is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution at EL1 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU DCISW 4 4 4 Trap execution of any of the following AArch64 instructions at EL1 to EL2: DC ISW. DC IGSW, if FEAT_MTE2 is implemented. DC IGDSW, if FEAT_MTE2 is implemented. 0b0 Execution of the specified instructions is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then execution at EL1 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU DCIVAC 3 3 3 Trap execution of any of the following AArch64 instructions at EL1 to EL2: DC IVAC. DC IGVAC, if FEAT_MTE2 is implemented. DC IGDVAC, if FEAT_MTE2 is implemented. 0b0 Execution of the specified instructions is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution at EL1 using AArch64 of any of the specified instructions is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU ICIVAU 2 2 2 Trap execution of IC IVAU at EL1 and EL0 using AArch64 to EL2. 0b0 Execution of IC IVAU is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution of IC IVAU at EL1 and EL0 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU ICIALLU 1 1 1 Trap execution of IC IALLU at EL1 using AArch64 to EL2. 0b0 Execution of IC IALLU is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution of IC IALLU at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU ICIALLUIS 0 0 0 Trap execution of IC IALLUIS at EL1 using AArch64 to EL2. 0b0 Execution of IC IALLUIS is not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then if the execution can be trapped, execution of IC IALLUIS at EL1 using AArch64 is trapped to EL2 and reported with EC syndrome value 0x18, unless the instruction generates a higher priority exception. '0' AU MRS <Xt>, HFGITR_EL2 if !(IsFeatureImplemented(FEAT_FGT) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x1C8); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = HFGITR_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = HFGITR_EL2(); end; MSR HFGITR_EL2, <Xt> if !(IsFeatureImplemented(FEAT_FGT) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x1C8) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else HFGITR_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then HFGITR_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel