HFGRTR2_EL2 Hypervisor Fine-Grained Read Trap Register 2 when FEAT_FGT2 is implemented and FEAT_AA64 is implemented Provides controls for traps of MRRS, MRS and MRC reads of System registers. Unknown If EL2 is not implemented, this register is RES0 from EL3. HFGRTR2_EL2 is a 64-bit register. 63 40 63:40 Reserved, RES0. ACTLR_EL1 39 39 0 Trap MRS reads of ACTLR_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 MRS reads of ACTLR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, then MRS reads of ACTLR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_SRMASK is implemented 39 39 39 Reserved, RES0. Otherwise 38 15 38:15 Reserved, RES0. nACTLRALIAS_EL1 14 14 0 Trap MRS reads of ACTLRALIAS_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MRS reads of ACTLRALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of ACTLRALIAS_EL1 are not trapped by this mechanism. '0' AU When FEAT_SRMASK is implemented 14 14 14 Reserved, RES0. Otherwise nACTLRMASK_EL1 13 13 0 Trap MRS reads of ACTLRMASK_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MRS reads of ACTLRMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of ACTLRMASK_EL1 are not trapped by this mechanism. '0' AU When FEAT_SRMASK is implemented 13 13 13 Reserved, RES0. Otherwise nTCR2ALIAS_EL1 12 12 0 Trap MRS reads of TCR2ALIAS_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MRS reads of TCR2ALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of TCR2ALIAS_EL1 are not trapped by this mechanism. '0' AU When FEAT_SRMASK is implemented 12 12 12 Reserved, RES0. Otherwise nTCRALIAS_EL1 11 11 0 Trap MRS reads of TCRALIAS_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MRS reads of TCRALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of TCRALIAS_EL1 are not trapped by this mechanism. '0' AU When FEAT_SRMASK is implemented 11 11 11 Reserved, RES0. Otherwise nSCTLR2ALIAS_EL1 10 10 0 Trap MRS reads of SCTLR2ALIAS_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MRS reads of SCTLR2ALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of SCTLR2ALIAS_EL1 are not trapped by this mechanism. '0' AU When FEAT_SRMASK is implemented 10 10 10 Reserved, RES0. Otherwise nSCTLRALIAS_EL1 9 9 0 Trap MRS reads of SCTLRALIAS_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MRS reads of SCTLRALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of SCTLRALIAS_EL1 are not trapped by this mechanism. '0' AU When FEAT_SRMASK is implemented 9 9 9 Reserved, RES0. Otherwise nCPACRALIAS_EL1 8 8 0 Trap MRS reads of CPACRALIAS_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MRS reads of CPACRALIAS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of CPACRALIAS_EL1 are not trapped by this mechanism. '0' AU When FEAT_SRMASK is implemented 8 8 8 Reserved, RES0. Otherwise nTCR2MASK_EL1 7 7 0 Trap MRS reads of TCR2MASK_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MRS reads of TCR2MASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of TCR2MASK_EL1 are not trapped by this mechanism. '0' AU When FEAT_SRMASK is implemented 7 7 7 Reserved, RES0. Otherwise nTCRMASK_EL1 6 6 0 Trap MRS reads of TCRMASK_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MRS reads of TCRMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of TCRMASK_EL1 are not trapped by this mechanism. '0' AU When FEAT_SRMASK is implemented 6 6 6 Reserved, RES0. Otherwise nSCTLR2MASK_EL1 5 5 0 Trap MRS reads of SCTLR2MASK_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MRS reads of SCTLR2MASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of SCTLR2MASK_EL1 are not trapped by this mechanism. '0' AU When FEAT_SRMASK is implemented 5 5 5 Reserved, RES0. Otherwise nSCTLRMASK_EL1 4 4 0 Trap MRS reads of SCTLRMASK_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MRS reads of SCTLRMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of SCTLRMASK_EL1 are not trapped by this mechanism. '0' AU When FEAT_SRMASK is implemented 4 4 4 Reserved, RES0. Otherwise nCPACRMASK_EL1 3 3 0 Trap MRS reads of CPACRMASK_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MRS reads of CPACRMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of CPACRMASK_EL1 are not trapped by this mechanism. '0' AU When FEAT_SRMASK is implemented 3 3 3 Reserved, RES0. Otherwise nRCWSMASK_EL1 2 2 0 Trap MRS or MRRS reads of RCWSMASK_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then unless the read generates a higher priority exception: MRS reads of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRRS reads of RCWSMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x14. 0b1 MRS and MRRS reads of RCWSMASK_EL1 are not trapped by this mechanism. '0' AU When FEAT_THE is implemented 2 2 2 Reserved, RES0. Otherwise nERXGSR_EL1 1 1 0 Trap MRS reads of ERXGSR_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. Accessing this field has the following behavior: This field is permitted to be RES0 if all of the following are true: ERRSELR_EL1 and all ERX* registers are implemented as UNDEFINED or RAZ/WI. ERRIDR_EL1.NUM is zero. 0b0 If EL2 is implemented and enabled in the current Security state, then MRS reads of ERXGSR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of ERXGSR_EL1 are not trapped by this mechanism. '0' AU When FEAT_RASv2 is implemented 1 1 1 Reserved, RES0. Otherwise nPFAR_EL1 0 0 0 Trap MRS reads of PFAR_EL1 at EL1 using AArch64 to EL2. This field is ignored by the PE and treated as zero when all of the following are true: EL3 is implemented. SCR_EL3.FGTEn2 == 0. 0b0 If EL2 is implemented and enabled in the current Security state, then MRS reads of PFAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of PFAR_EL1 are not trapped by this mechanism. '0' AU When FEAT_PFAR is implemented 0 0 0 Reserved, RES0. Otherwise MRS <Xt>, HFGRTR2_EL2 if !(IsFeatureImplemented(FEAT_FGT2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x2C0); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn2 == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = HFGRTR2_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = HFGRTR2_EL2(); end; MSR HFGRTR2_EL2, <Xt> if !(IsFeatureImplemented(FEAT_FGT2) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x2C0) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn2 == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn2 == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else HFGRTR2_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then HFGRTR2_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel