HFGRTR_EL2 Hypervisor Fine-Grained Read Trap Register when FEAT_FGT is implemented and FEAT_AA64 is implemented EL2 Provides controls for traps of MRRS, MRS and MRC reads of System registers. Unknown If EL2 is not implemented, this register is RES0 from EL3. HFGRTR_EL2 is a 64-bit register. nAMAIR2_EL1 63 63 0 Trap MRS reads of AMAIR2_EL1 at EL1 using AArch64 to EL2. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of AMAIR2_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of AMAIR2_EL1 are not trapped by this mechanism. '0' AU When FEAT_AIE is implemented 63 63 63 Reserved, RES0. Otherwise nMAIR2_EL1 62 62 0 Trap MRS reads of MAIR2_EL1 at EL1 using AArch64 to EL2. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of MAIR2_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of MAIR2_EL1 are not trapped by this mechanism. '0' AU When FEAT_AIE is implemented 62 62 62 Reserved, RES0. Otherwise nS2POR_EL1 61 61 0 Trap MRS reads of S2POR_EL1 at EL1 using AArch64 to EL2. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of S2POR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of S2POR_EL1 are not trapped by this mechanism. '0' AU When FEAT_S2POE is implemented 61 61 61 Reserved, RES0. Otherwise nPOR_EL1 60 60 0 Trap MRS reads of POR_EL1 at EL1 using AArch64 to EL2. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of POR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of POR_EL1 are not trapped by this mechanism. '0' AU When FEAT_S1POE is implemented 60 60 60 Reserved, RES0. Otherwise nPOR_EL0 59 59 0 Trap MRS reads of POR_EL0 at EL1 and EL0 using AArch64 to EL2. 0b0 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of POR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of POR_EL0 are not trapped by this mechanism. '0' AU When FEAT_S1POE is implemented 59 59 59 Reserved, RES0. Otherwise nPIR_EL1 58 58 0 Trap MRS reads of PIR_EL1 at EL1 using AArch64 to EL2. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of PIR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of PIR_EL1 are not trapped by this mechanism. '0' AU When FEAT_S1PIE is implemented 58 58 58 Reserved, RES0. Otherwise nPIRE0_EL1 57 57 0 Trap MRS reads of PIRE0_EL1 at EL1 using AArch64 to EL2. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of PIRE0_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of PIRE0_EL1 are not trapped by this mechanism. '0' AU When FEAT_S1PIE is implemented 57 57 57 Reserved, RES0. Otherwise nRCWMASK_EL1 56 56 0 Trap MRS or MRRS reads of RCWMASK_EL1 at EL1 using AArch64 to EL2. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the read generates a higher priority exception: MRS reads of RCWMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRRS reads of RCWMASK_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x14. 0b1 MRS and MRRS reads of RCWMASK_EL1 are not trapped by this mechanism. '0' AU When FEAT_THE is implemented 56 56 56 Reserved, RES0. Otherwise nTPIDR2_EL0 55 55 0 Trap MRS reads of TPIDR2_EL0 at EL1 and EL0 using AArch64 to EL2. 0b0 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TPIDR2_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of TPIDR2_EL0 are not trapped by this mechanism. '0' AU When FEAT_SME is implemented 55 55 55 Reserved, RES0. Otherwise nSMPRI_EL1 54 54 0 Trap MRS reads of SMPRI_EL1 at EL1 using AArch64 to EL2. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of SMPRI_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of SMPRI_EL1 are not trapped by this mechanism. '0' AU When FEAT_SME is implemented 54 54 54 Reserved, RES0. Otherwise nGCS_EL1 53 53 0 Trap MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2: GCSCR_EL1. GCSPR_EL1. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of the specified System registers are not trapped by this mechanism. '0' AU When FEAT_GCS is implemented 53 53 53 Reserved, RES0. Otherwise nGCS_EL0 52 52 0 Trap MRS reads at EL1 and EL0 using AArch64 of any of the following AArch64 System registers to EL2: GCSCRE0_EL1, at EL1 only. GCSPR_EL0. 0b0 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 and EL0 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of the specified System registers are not trapped by this mechanism. '0' AU When FEAT_GCS is implemented 52 52 52 Reserved, RES0. Otherwise 51 51 51 Reserved, RES0. nACCDATA_EL1 50 50 0 Trap MRS reads of ACCDATA_EL1 at EL1 using AArch64 to EL2. 0b0 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ACCDATA_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. 0b1 MRS reads of ACCDATA_EL1 are not trapped by this mechanism. '0' AU When FEAT_LS64_ACCDATA is implemented 50 50 50 Reserved, RES0. Otherwise ERXADDR_EL1 49 49 0 Trap MRS reads of ERXADDR_EL1 at EL1 using AArch64 to EL2. Accessing this field has the following behavior: This field is permitted to be RES0 if all of the following are true: ERRSELR_EL1 and all ERX* registers are implemented as UNDEFINED or RAZ/WI. ERRIDR_EL1.NUM is zero. 0b0 MRS reads of ERXADDR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERXADDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_RAS is implemented 49 49 49 Reserved, RES0. Otherwise ERXPFGCDN_EL1 48 48 0 Trap MRS reads of ERXPFGCDN_EL1 at EL1 using AArch64 to EL2. Accessing this field has the following behavior: This field is permitted to be RES0 if all of the following are true: ERRSELR_EL1 and all ERX* registers are implemented as UNDEFINED or RAZ/WI. ERRIDR_EL1.NUM is zero. 0b0 MRS reads of ERXPFGCDN_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERXPFGCDN_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_RASv1p1 is implemented 48 48 48 Reserved, RES0. Otherwise ERXPFGCTL_EL1 47 47 0 Trap MRS reads of ERXPFGCTL_EL1 at EL1 using AArch64 to EL2. Accessing this field has the following behavior: This field is permitted to be RES0 if all of the following are true: ERRSELR_EL1 and all ERX* registers are implemented as UNDEFINED or RAZ/WI. ERRIDR_EL1.NUM is zero. 0b0 MRS reads of ERXPFGCTL_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERXPFGCTL_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_RASv1p1 is implemented 47 47 47 Reserved, RES0. Otherwise ERXPFGF_EL1 46 46 0 Trap MRS reads of ERXPFGF_EL1 at EL1 using AArch64 to EL2. Accessing this field has the following behavior: This field is permitted to be RES0 if all of the following are true: ERRSELR_EL1 and all ERX* registers are implemented as UNDEFINED or RAZ/WI. ERRIDR_EL1.NUM is zero. 0b0 MRS reads of ERXPFGF_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERXPFGF_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_RASv1p1 is implemented 46 46 46 Reserved, RES0. Otherwise ERXMISCn_EL1 45 45 0 Trap MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2: ERXMISC0_EL1. ERXMISC1_EL1. ERXMISC2_EL1. ERXMISC3_EL1. Accessing this field has the following behavior: This field is permitted to be RES0 if all of the following are true: ERRSELR_EL1 and all ERX* registers are implemented as UNDEFINED or RAZ/WI. ERRIDR_EL1.NUM is zero. 0b0 MRS reads of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_RAS is implemented 45 45 45 Reserved, RES0. Otherwise ERXSTATUS_EL1 44 44 0 Trap MRS reads of ERXSTATUS_EL1 at EL1 using AArch64 to EL2. Accessing this field has the following behavior: This field is permitted to be RES0 if all of the following are true: ERRSELR_EL1 and all ERX* registers are implemented as UNDEFINED or RAZ/WI. ERRIDR_EL1.NUM is zero. 0b0 MRS reads of ERXSTATUS_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERXSTATUS_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_RAS is implemented 44 44 44 Reserved, RES0. Otherwise ERXCTLR_EL1 43 43 0 Trap MRS reads of ERXCTLR_EL1 at EL1 using AArch64 to EL2. Accessing this field has the following behavior: This field is permitted to be RES0 if all of the following are true: ERRSELR_EL1 and all ERX* registers are implemented as UNDEFINED or RAZ/WI. ERRIDR_EL1.NUM is zero. 0b0 MRS reads of ERXCTLR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERXCTLR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_RAS is implemented 43 43 43 Reserved, RES0. Otherwise ERXFR_EL1 42 42 0 Trap MRS reads of ERXFR_EL1 at EL1 using AArch64 to EL2. Accessing this field has the following behavior: This field is permitted to be RES0 if all of the following are true: ERRSELR_EL1 and all ERX* registers are implemented as UNDEFINED or RAZ/WI. ERRIDR_EL1.NUM is zero. 0b0 MRS reads of ERXFR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERXFR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_RAS is implemented 42 42 42 Reserved, RES0. Otherwise ERRSELR_EL1 41 41 0 Trap MRS reads of ERRSELR_EL1 at EL1 using AArch64 to EL2. Accessing this field has the following behavior: This field is permitted to be RES0 if all of the following are true: ERRSELR_EL1 and all ERX* registers are implemented as UNDEFINED or RAZ/WI. ERRIDR_EL1.NUM is zero. 0b0 MRS reads of ERRSELR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERRSELR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_RAS is implemented 41 41 41 Reserved, RES0. Otherwise ERRIDR_EL1 40 40 0 Trap MRS reads of ERRIDR_EL1 at EL1 using AArch64 to EL2. Accessing this field has the following behavior: This field is permitted to be RES0 if all of the following are true: ERRSELR_EL1 and all ERX* registers are implemented as UNDEFINED or RAZ/WI. ERRIDR_EL1.NUM is zero. 0b0 MRS reads of ERRIDR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ERRIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_RAS is implemented 40 40 40 Reserved, RES0. Otherwise ICC_IGRPENn_EL1 39 39 0 Trap MRS reads of ICC_IGRPEN<n>_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of ICC_IGRPEN<n>_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ICC_IGRPEN<n>_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When GICv3 is implemented 39 39 39 Reserved, RES0. Otherwise VBAR_EL1 38 38 38 Trap MRS reads of VBAR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of VBAR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of VBAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU TTBR1_EL1 37 37 37 Trap MRS or MRRS reads of TTBR1_EL1 at EL1 using AArch64 to EL2. 0b0 MRS and MRRS reads of TTBR1_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the read generates a higher priority exception: MRS reads of TTBR1_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRRS reads of TTBR1_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x14. '0' AU TTBR0_EL1 36 36 36 Trap MRS or MRRS reads of TTBR0_EL1 at EL1 using AArch64 to EL2. 0b0 MRS and MRRS reads of TTBR0_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the read generates a higher priority exception: MRS reads of TTBR0_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRRS reads of TTBR0_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x14. '0' AU TPIDR_EL0 35 35 35 Trap MRS reads of TPIDR_EL0 at EL1 and EL0 using AArch64 and MRC reads of TPIDRURW at EL0 using AArch32 when EL1 is using AArch64 to EL2. 0b0 MRS reads of TPIDR_EL0 at EL1 and EL0 using AArch64 and MRC reads of TPIDRURW at EL0 using AArch32 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the read generates a higher priority exception: MRS reads of TPIDR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRC reads of TPIDRURW at EL0 using AArch32 when EL1 is using AArch64 are trapped to EL2 and reported with EC syndrome value 0x03. '0' AU TPIDRRO_EL0 34 34 34 Trap MRS reads of TPIDRRO_EL0 at EL1 and EL0 using AArch64 and MRC reads of TPIDRURO at EL0 using AArch32 when EL1 is using AArch64 to EL2. 0b0 MRS reads of TPIDRRO_EL0 at EL1 and EL0 using AArch64 and MRC reads of TPIDRURO at EL0 using AArch32 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the read generates a higher priority exception: MRS reads of TPIDRRO_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRC reads of TPIDRURO at EL0 using AArch32 when EL1 is using AArch64 are trapped to EL2 and reported with EC syndrome value 0x03. '0' AU TPIDR_EL1 33 33 33 Trap MRS reads of TPIDR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of TPIDR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of TPIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU TCR_EL1 32 32 32 Trap MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2: TCR_EL1. TCR2_EL1, if FEAT_TCR2 is implemented. 0b0 MRS reads of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU SCXTNUM_EL0 31 31 0 Trap MRS reads of SCXTNUM_EL0 at EL1 and EL0 using AArch64 to EL2. 0b0 MRS reads of SCXTNUM_EL0 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of SCXTNUM_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented 31 31 31 Reserved, RES0. Otherwise SCXTNUM_EL1 30 30 0 Trap MRS reads of SCXTNUM_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of SCXTNUM_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of SCXTNUM_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_CSV2_2 is implemented or FEAT_CSV2_1p2 is implemented 30 30 30 Reserved, RES0. Otherwise SCTLR_EL1 29 29 29 Trap MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2: SCTLR_EL1. SCTLR2_EL1, if FEAT_SCTLR2 is implemented. 0b0 MRS reads of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU REVIDR_EL1 28 28 28 Trap MRS reads of REVIDR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of REVIDR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of REVIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU PAR_EL1 27 27 27 Trap MRS or MRRS reads of PAR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS and MRRS reads of PAR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then unless the read generates a higher priority exception: MRS reads of PAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18. MRRS reads of PAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x14. '0' AU MPIDR_EL1 26 26 26 Trap MRS reads of MPIDR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of MPIDR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of MPIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU MIDR_EL1 25 25 25 Trap MRS reads of MIDR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of MIDR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of MIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU MAIR_EL1 24 24 24 Trap MRS reads of MAIR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of MAIR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of MAIR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU LORSA_EL1 23 23 0 Trap MRS reads of LORSA_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of LORSA_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of LORSA_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_LOR is implemented 23 23 23 Reserved, RES0. Otherwise LORN_EL1 22 22 0 Trap MRS reads of LORN_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of LORN_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of LORN_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_LOR is implemented 22 22 22 Reserved, RES0. Otherwise LORID_EL1 21 21 0 Trap MRS reads of LORID_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of LORID_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of LORID_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_LOR is implemented 21 21 21 Reserved, RES0. Otherwise LOREA_EL1 20 20 0 Trap MRS reads of LOREA_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of LOREA_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of LOREA_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_LOR is implemented 20 20 20 Reserved, RES0. Otherwise LORC_EL1 19 19 0 Trap MRS reads of LORC_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of LORC_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of LORC_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_LOR is implemented 19 19 19 Reserved, RES0. Otherwise ISR_EL1 18 18 18 Trap MRS reads of ISR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of ISR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ISR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU FAR_EL1 17 17 17 Trap MRS reads of FAR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of FAR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of FAR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU ESR_EL1 16 16 16 Trap MRS reads of ESR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of ESR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of ESR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU DCZID_EL0 15 15 15 Trap MRS reads of DCZID_EL0 at EL1 and EL0 using AArch64 to EL2. 0b0 MRS reads of DCZID_EL0 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of DCZID_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU CTR_EL0 14 14 14 Trap MRS reads of CTR_EL0 at EL1 and EL0 using AArch64 to EL2. 0b0 MRS reads of CTR_EL0 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, the Effective value of HCR_EL2.{E2H, TGE} is not {1, 1}, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of CTR_EL0 at EL1 and EL0 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU CSSELR_EL1 13 13 13 Trap MRS reads of CSSELR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of CSSELR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of CSSELR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU CPACR_EL1 12 12 12 Trap MRS reads of CPACR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of CPACR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of CPACR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU CONTEXTIDR_EL1 11 11 11 Trap MRS reads of CONTEXTIDR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of CONTEXTIDR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of CONTEXTIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU CLIDR_EL1 10 10 10 Trap MRS reads of CLIDR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of CLIDR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of CLIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU CCSIDR_EL1 9 9 9 Trap MRS reads of CCSIDR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of CCSIDR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of CCSIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU APIBKey 8 8 0 Trap MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2: APIBKeyHi_EL1. APIBKeyLo_EL1. 0b0 MRS reads of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_PAuth is implemented 8 8 8 Reserved, RES0. Otherwise APIAKey 7 7 0 Trap MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2: APIAKeyHi_EL1. APIAKeyLo_EL1. 0b0 MRS reads of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_PAuth is implemented 7 7 7 Reserved, RES0. Otherwise APGAKey 6 6 0 Trap MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2: APGAKeyHi_EL1. APGAKeyLo_EL1. 0b0 MRS reads of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_PAuth is implemented 6 6 6 Reserved, RES0. Otherwise APDBKey 5 5 0 Trap MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2: APDBKeyHi_EL1. APDBKeyLo_EL1. 0b0 MRS reads of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_PAuth is implemented 5 5 5 Reserved, RES0. Otherwise APDAKey 4 4 0 Trap MRS reads at EL1 using AArch64 of any of the following AArch64 System registers to EL2: APDAKeyHi_EL1. APDAKeyLo_EL1. 0b0 MRS reads of the specified System registers are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads at EL1 using AArch64 of any of the specified System registers are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU When FEAT_PAuth is implemented 4 4 4 Reserved, RES0. Otherwise AMAIR_EL1 3 3 3 Trap MRS reads of AMAIR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of AMAIR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of AMAIR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU AIDR_EL1 2 2 2 Trap MRS reads of AIDR_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of AIDR_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of AIDR_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU AFSR1_EL1 1 1 1 Trap MRS reads of AFSR1_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of AFSR1_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of AFSR1_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU AFSR0_EL1 0 0 0 Trap MRS reads of AFSR0_EL1 at EL1 using AArch64 to EL2. 0b0 MRS reads of AFSR0_EL1 are not trapped by this mechanism. 0b1 If EL2 is implemented and enabled in the current Security state, and either EL3 is not implemented or SCR_EL3.FGTEn == 1, then MRS reads of AFSR0_EL1 at EL1 using AArch64 are trapped to EL2 and reported with EC syndrome value 0x18, unless the read generates a higher priority exception. '0' AU MRS <Xt>, HFGRTR_EL2 if !(IsFeatureImplemented(FEAT_FGT) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x1B8); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = HFGRTR_EL2(); end; elsif PSTATE.EL == EL3 then X{64}(t) = HFGRTR_EL2(); end; MSR HFGRTR_EL2, <Xt> if !(IsFeatureImplemented(FEAT_FGT) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x1B8) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FGTEn == '0' then Undefined(); elsif HaveEL(EL3) && SCR_EL3().FGTEn == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else HFGRTR_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then HFGRTR_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel