HSTR_EL2 Hypervisor System Trap Register when FEAT_AA64 is implemented HSTR Architectural AArch32 31 0 31 0 31 0 31 0 Controls trapping to EL2 of EL1 or lower AArch32 accesses to the System register in the coproc == 0b1111 encoding space, by the CRn value used to access the register using MCR or MRC instruction. When the register is accessible using an MCRR or MRRC instruction, this is the CRm value used to access the register. Virt If EL2 is not implemented, this register is RES0 from EL3. This register has no effect if EL2 is not enabled in the current Security state. HSTR_EL2 is a 64-bit register. When FEAT_AA32 is implemented 63 16 63:16, 14, 4 Reserved, RES0. 63 16 14 14 4 4 T<n> 15 15 15, 13:5, 3:0 The remaining fields control whether EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == 0b1111 encoding space, are trapped to EL2 as follows: MCR or MRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x03, unless the access is UNDEFINED. MCRR or MRRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x04, unless the access is UNDEFINED. For example, when HSTR_EL2.T7 is 1, for instructions executed at EL1: An MCR or MRC instruction with coproc set to 0b1111 and <CRn> set to c7 is trapped to EL2. An MCRR or MRRC instruction with coproc set to 0b1111 and <CRm> set to c7 is trapped to EL2. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit. 15 15 13 5 3 0 15 15 13 5 3 0 T<n> 0b0 This control has no effect on EL0 or EL1 accesses to System registers. 0b1 System registers in the coproc == 0b1111 encoding space and CRn == <n> or CRm == <n> where T<n> is the name of this field, are trapped as follows: An EL1 MCR or MRC access is trapped to EL2. An EL0 MCR or MRC access is trapped to EL2, if the access is not UNDEFINED when the value of this field is 0. An EL1 MCRR or MRRC access is trapped to EL2. An EL0 MCRR or MRRC access is trapped to EL2, if the access is not UNDEFINED when the value of this field is 0. It is IMPLEMENTATION DEFINED whether an EL0 access using AArch32 is trapped to EL2, or is UNDEFINED. If the access is UNDEFINED, and generates an exception that is taken to EL1 or EL2 using AArch64, this is reported with EC syndrome value 0x00. Arm expects that trapping to EL2 of EL0 accesses to these registers is unusual and used only when the hypervisor must virtualize EL0 operation. Arm recommends that, whenever possible, EL0 accesses to these registers behave as they would if the implementation did not include EL2. This means that, if the architecture does not support the EL0 access, then the register access instruction is treated as UNDEFINED and generates an exception that is taken to EL1. AU T15 15 15 13 The remaining fields control whether EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == 0b1111 encoding space, are trapped to EL2 as follows: MCR or MRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x03, unless the access is UNDEFINED. MCRR or MRRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x04, unless the access is UNDEFINED. For example, when HSTR_EL2.T7 is 1, for instructions executed at EL1: An MCR or MRC instruction with coproc set to 0b1111 and <CRn> set to c7 is trapped to EL2. An MCRR or MRRC instruction with coproc set to 0b1111 and <CRm> set to c7 is trapped to EL2. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit. 14 14 63:16, 14, 4 Reserved, RES0. T13 13 13 13 The remaining fields control whether EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == 0b1111 encoding space, are trapped to EL2 as follows: MCR or MRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x03, unless the access is UNDEFINED. MCRR or MRRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x04, unless the access is UNDEFINED. For example, when HSTR_EL2.T7 is 1, for instructions executed at EL1: An MCR or MRC instruction with coproc set to 0b1111 and <CRn> set to c7 is trapped to EL2. An MCRR or MRRC instruction with coproc set to 0b1111 and <CRm> set to c7 is trapped to EL2. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit. T12 12 12 12 The remaining fields control whether EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == 0b1111 encoding space, are trapped to EL2 as follows: MCR or MRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x03, unless the access is UNDEFINED. MCRR or MRRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x04, unless the access is UNDEFINED. For example, when HSTR_EL2.T7 is 1, for instructions executed at EL1: An MCR or MRC instruction with coproc set to 0b1111 and <CRn> set to c7 is trapped to EL2. An MCRR or MRRC instruction with coproc set to 0b1111 and <CRm> set to c7 is trapped to EL2. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit. T11 11 11 11 The remaining fields control whether EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == 0b1111 encoding space, are trapped to EL2 as follows: MCR or MRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x03, unless the access is UNDEFINED. MCRR or MRRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x04, unless the access is UNDEFINED. For example, when HSTR_EL2.T7 is 1, for instructions executed at EL1: An MCR or MRC instruction with coproc set to 0b1111 and <CRn> set to c7 is trapped to EL2. An MCRR or MRRC instruction with coproc set to 0b1111 and <CRm> set to c7 is trapped to EL2. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit. T10 10 10 10 The remaining fields control whether EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == 0b1111 encoding space, are trapped to EL2 as follows: MCR or MRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x03, unless the access is UNDEFINED. MCRR or MRRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x04, unless the access is UNDEFINED. For example, when HSTR_EL2.T7 is 1, for instructions executed at EL1: An MCR or MRC instruction with coproc set to 0b1111 and <CRn> set to c7 is trapped to EL2. An MCRR or MRRC instruction with coproc set to 0b1111 and <CRm> set to c7 is trapped to EL2. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit. T9 9 9 9 The remaining fields control whether EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == 0b1111 encoding space, are trapped to EL2 as follows: MCR or MRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x03, unless the access is UNDEFINED. MCRR or MRRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x04, unless the access is UNDEFINED. For example, when HSTR_EL2.T7 is 1, for instructions executed at EL1: An MCR or MRC instruction with coproc set to 0b1111 and <CRn> set to c7 is trapped to EL2. An MCRR or MRRC instruction with coproc set to 0b1111 and <CRm> set to c7 is trapped to EL2. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit. T8 8 8 8 The remaining fields control whether EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == 0b1111 encoding space, are trapped to EL2 as follows: MCR or MRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x03, unless the access is UNDEFINED. MCRR or MRRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x04, unless the access is UNDEFINED. For example, when HSTR_EL2.T7 is 1, for instructions executed at EL1: An MCR or MRC instruction with coproc set to 0b1111 and <CRn> set to c7 is trapped to EL2. An MCRR or MRRC instruction with coproc set to 0b1111 and <CRm> set to c7 is trapped to EL2. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit. T7 7 7 7 The remaining fields control whether EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == 0b1111 encoding space, are trapped to EL2 as follows: MCR or MRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x03, unless the access is UNDEFINED. MCRR or MRRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x04, unless the access is UNDEFINED. For example, when HSTR_EL2.T7 is 1, for instructions executed at EL1: An MCR or MRC instruction with coproc set to 0b1111 and <CRn> set to c7 is trapped to EL2. An MCRR or MRRC instruction with coproc set to 0b1111 and <CRm> set to c7 is trapped to EL2. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit. T6 6 6 6 The remaining fields control whether EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == 0b1111 encoding space, are trapped to EL2 as follows: MCR or MRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x03, unless the access is UNDEFINED. MCRR or MRRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x04, unless the access is UNDEFINED. For example, when HSTR_EL2.T7 is 1, for instructions executed at EL1: An MCR or MRC instruction with coproc set to 0b1111 and <CRn> set to c7 is trapped to EL2. An MCRR or MRRC instruction with coproc set to 0b1111 and <CRm> set to c7 is trapped to EL2. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit. T5 5 5 5 The remaining fields control whether EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == 0b1111 encoding space, are trapped to EL2 as follows: MCR or MRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x03, unless the access is UNDEFINED. MCRR or MRRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x04, unless the access is UNDEFINED. For example, when HSTR_EL2.T7 is 1, for instructions executed at EL1: An MCR or MRC instruction with coproc set to 0b1111 and <CRn> set to c7 is trapped to EL2. An MCRR or MRRC instruction with coproc set to 0b1111 and <CRm> set to c7 is trapped to EL2. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit. 4 4 63:16, 14, 4 Reserved, RES0. T3 3 3 3 The remaining fields control whether EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == 0b1111 encoding space, are trapped to EL2 as follows: MCR or MRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x03, unless the access is UNDEFINED. MCRR or MRRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x04, unless the access is UNDEFINED. For example, when HSTR_EL2.T7 is 1, for instructions executed at EL1: An MCR or MRC instruction with coproc set to 0b1111 and <CRn> set to c7 is trapped to EL2. An MCRR or MRRC instruction with coproc set to 0b1111 and <CRm> set to c7 is trapped to EL2. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit. T2 2 2 2 The remaining fields control whether EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == 0b1111 encoding space, are trapped to EL2 as follows: MCR or MRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x03, unless the access is UNDEFINED. MCRR or MRRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x04, unless the access is UNDEFINED. For example, when HSTR_EL2.T7 is 1, for instructions executed at EL1: An MCR or MRC instruction with coproc set to 0b1111 and <CRn> set to c7 is trapped to EL2. An MCRR or MRRC instruction with coproc set to 0b1111 and <CRm> set to c7 is trapped to EL2. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit. T1 1 1 1 The remaining fields control whether EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == 0b1111 encoding space, are trapped to EL2 as follows: MCR or MRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x03, unless the access is UNDEFINED. MCRR or MRRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x04, unless the access is UNDEFINED. For example, when HSTR_EL2.T7 is 1, for instructions executed at EL1: An MCR or MRC instruction with coproc set to 0b1111 and <CRn> set to c7 is trapped to EL2. An MCRR or MRRC instruction with coproc set to 0b1111 and <CRm> set to c7 is trapped to EL2. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit. T0 0 0 0 The remaining fields control whether EL0 and EL1 accesses, using MCR, MRC, MCRR, and MRRC instructions, to the System registers in the coproc == 0b1111 encoding space, are trapped to EL2 as follows: MCR or MRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x03, unless the access is UNDEFINED. MCRR or MRRC accesses to these registers that are trapped to EL2 are reported using EC syndrome value 0x04, unless the access is UNDEFINED. For example, when HSTR_EL2.T7 is 1, for instructions executed at EL1: An MCR or MRC instruction with coproc set to 0b1111 and <CRn> set to c7 is trapped to EL2. An MCRR or MRRC instruction with coproc set to 0b1111 and <CRm> set to c7 is trapped to EL2. When the Effective value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this bit. 63 0 63:0 Reserved, RES0. When FEAT_AA32 is implemented MRS <Xt>, HSTR_EL2 if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x080); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then X{64}(t) = HSTR_EL2(); elsif PSTATE.EL == EL3 then X{64}(t) = HSTR_EL2(); end; MSR HSTR_EL2, <Xt> if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x080) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then HSTR_EL2() = X{64}(t); elsif PSTATE.EL == EL3 then HSTR_EL2() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel