IC IALLU Instruction Cache Invalidate All to PoU when FEAT_AA64 is implemented ICIALLU Functional AArch32 Invalidate all instruction caches of the PE executing the instruction to the Point of Unification. Cache IC IALLU is a 64-bit System instruction. The Rt field should be set to 0b11111. If the Rt field is not set to 0b11111, it is CONSTRAINED UNPREDICTABLE whether: The instruction is UNDEFINED. The instruction behaves as if the Rt field is set to 0b11111. This system instruction is an alias of the SYS instruction. The following pseudocode describes traps which apply to the System instruction. For information about changes to the scope of the invalidation to the instruction under different conditions, see AArch64_IC() in the Pseudocode for AArch64 operation. IC IALLU{, <Xt>} if !IsFeatureImplemented(FEAT_AA64) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if !AArch64_CanTrapIC(CacheType_Instruction, CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); elsif EL2Enabled() && HCR_EL2().TPU == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().TOCU == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGITR_EL2().ICIALLU == '1' then AArch64_SystemAccessTrap(EL2, 0x18); else if AArch64_TreatICAsNOP(CacheType_Instruction, CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); else AArch64_IC(CacheOpScope_ALLU); end; end; elsif PSTATE.EL == EL2 then if !AArch64_CanTrapIC(CacheType_Instruction, CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); else if AArch64_TreatICAsNOP(CacheType_Instruction, CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); else AArch64_IC(CacheOpScope_ALLU); end; end; elsif PSTATE.EL == EL3 then if AArch64_TreatICAsNOP(CacheType_Instruction, CacheOp_Invalidate, CacheOpScope_PoU) then ExecuteAsNOP(); else AArch64_IC(CacheOpScope_ALLU); end; end; 2026-03-26 20:27:25 2026-03_rel