ICC_CTLR_EL1 Interrupt Controller Control Register (EL1) when GICv3 is implemented and FEAT_AA64 is implemented ICC_CTLR Architectural AArch32 31 0 ICC_CTLR_EL1_S 31 0 ICC_CTLR_S 31 0 31 0 ICC_CTLR Architectural AArch32 31 0 ICC_CTLR_EL1_NS 31 0 ICC_CTLR_NS 31 0 31 0 Controls aspects of the behavior of the GIC CPU interface and provides information about the features implemented. GIC control registers GIC Identification Registers This register is banked between ICC_CTLR_EL1 and ICC_CTLR_EL1_S and ICC_CTLR_EL1_NS. ICC_CTLR_EL1 is a 64-bit register. This register has the following instances: ICC_CTLR_EL1, when EL3 is not implemented. ICC_CTLR_EL1_S, when EL3 is implemented. ICC_CTLR_EL1_NS, when EL3 is implemented. 63 20 63:20 Reserved, RES0. ExtRange 19 19 19 Extended INTID range (read-only). If EL3 is implemented, ICC_CTLR_EL1.ExtRange is an alias of ICC_CTLR_EL3.ExtRange. 0b0 CPU interface does not support INTIDs in the range 1024..8191. Behavior is UNPREDICTABLE if the IRI delivers an interrupt in the range 1024 to 8191 to the CPU interface. Arm strongly recommends that the IRI is not configured to deliver interrupts in this range to a PE that does not support them. 0b1 CPU interface supports INTIDs in the range 1024..8191 All INTIDs in the range 1024..8191 are treated as requiring deactivation. RSS 18 18 18 Range Selector Support. Possible values are: This bit is read-only. 0b0 Targeted SGIs with affinity level 0 values of 0 - 15 are supported. 0b1 Targeted SGIs with affinity level 0 values of 0 - 255 are supported. 17 16 17:16 Reserved, RES0. A3V 15 15 15 Affinity 3 Valid. Read-only and writes are ignored. Possible values are: If EL3 is implemented, this bit is an alias of ICC_CTLR_EL3.A3V. 0b0 The CPU interface logic only supports zero values of Affinity 3 in SGI generation System registers. 0b1 The CPU interface logic supports nonzero values of Affinity 3 in SGI generation System registers. SEIS 14 14 14 SEI Support. Read-only and writes are ignored. Indicates whether the CPU interface supports local generation of SEIs: If EL3 is implemented, this bit is an alias of ICC_CTLR_EL3.SEIS. 0b0 The CPU interface logic does not support local generation of SEIs. 0b1 The CPU interface logic supports local generation of SEIs. IDbits 13 11 13:11 Identifier bits. Read-only and writes are ignored. The number of physical interrupt identifier bits supported: All other values are reserved. If EL3 is implemented, this field is an alias of ICC_CTLR_EL3.IDbits. 0b000 16 bits. 0b001 24 bits. PRIbits 10 8 10:8 Priority bits. Read-only and writes are ignored. The number of priority bits implemented, minus one. An implementation that supports two Security states must implement at least 32 levels of physical priority (5 priority bits). An implementation that supports only a single Security state must implement at least 16 levels of physical priority (4 priority bits). This field always returns the number of priority bits implemented, regardless of the Security state of the access or the value of GICD_CTLR.DS.For physical accesses, this field determines the minimum value of ICC_BPR0_EL1. If EL3 is implemented, physical accesses return the value from ICC_CTLR_EL3.PRIbits. If EL3 is not implemented, physical accesses return the value from this field. 7 7 7 Reserved, RES0. PMHE 6 6 6 Priority Mask Hint Enable. Controls whether the priority mask register is used as a hint for interrupt distribution: If EL3 is implemented, this bit is an alias of ICC_CTLR_EL3.PMHE. Whether this bit can be written as part of an access to this register depends on the value of GICD_CTLR.DS: If GICD_CTLR.DS == 0, this bit is read-only. If GICD_CTLR.DS == 1, this bit is read/write. If EL3 is not implemented, it is IMPLEMENTATION DEFINED whether this bit is read-only or read/write: If this bit is read-only, an implementation can choose to make this field RAZ/WI or RAO/WI. If this bit is read/write, it resets to zero. 0b0 Disables use of ICC_PMR_EL1 as a hint for interrupt distribution. 0b1 Enables use of ICC_PMR_EL1 as a hint for interrupt distribution. 5 2 5:2 Reserved, RES0. EOImode 1 1 1 EOI mode for the current Security state. Controls whether a write to an End of Interrupt register also deactivates the interrupt: The Secure ICC_CTLR_EL1.EOImode is an alias of ICC_CTLR_EL3.EOImode_EL1S. The Non-secure ICC_CTLR_EL1.EOImode is an alias of ICC_CTLR_EL3.EOImode_EL1NS 0b0 ICC_EOIR0_EL1 and ICC_EOIR1_EL1 provide both priority drop and interrupt deactivation functionality. Accesses to ICC_DIR_EL1 are UNPREDICTABLE. 0b1 ICC_EOIR0_EL1 and ICC_EOIR1_EL1 provide priority drop functionality only. ICC_DIR_EL1 provides interrupt deactivation functionality. CBPR 0 0 0 Common Binary Point Register. Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 interrupts: If EL3 is implemented: This bit is an alias of ICC_CTLR_EL3.CBPR_EL1{S,NS} where S or NS corresponds to the current Security state. If GICD_CTLR.DS == 0, this bit is read-only. If GICD_CTLR.DS == 1, this bit is read/write. If EL3 is not implemented, this bit is read/write. 0b0 ICC_BPR0_EL1 determines the preemption group for Group 0 interrupts only. ICC_BPR1_EL1 determines the preemption group for Group 1 interrupts. 0b1 ICC_BPR0_EL1 determines the preemption group for both Group 0 and Group 1 interrupts. AU MRS <Xt>, ICC_CTLR_EL1 if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().FMO == '1' then X{64}(t) = ICV_CTLR_EL1(); elsif EL2Enabled() && HCR_EL2().IMO == '1' then X{64}(t) = ICV_CTLR_EL1(); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_CTLR_EL1_S(); else X{64}(t) = ICC_CTLR_EL1_NS(); end; else X{64}(t) = ICC_CTLR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_CTLR_EL1_S(); else X{64}(t) = ICC_CTLR_EL1_NS(); end; else X{64}(t) = ICC_CTLR_EL1(); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_CTLR_EL1_S(); else X{64}(t) = ICC_CTLR_EL1_NS(); end; end; end; MSR ICC_CTLR_EL1, <Xt> if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().FMO == '1' then ICV_CTLR_EL1() = X{64}(t); elsif EL2Enabled() && HCR_EL2().IMO == '1' then ICV_CTLR_EL1() = X{64}(t); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_CTLR_EL1_S() = X{64}(t); else ICC_CTLR_EL1_NS() = X{64}(t); end; else ICC_CTLR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_CTLR_EL1_S() = X{64}(t); else ICC_CTLR_EL1_NS() = X{64}(t); end; else ICC_CTLR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else if EffectiveSCR_EL3_NS() == '0' then ICC_CTLR_EL1_S() = X{64}(t); else ICC_CTLR_EL1_NS() = X{64}(t); end; end; end; 2026-03-26 20:27:25 2026-03_rel