ICC_CTLR_EL3 Interrupt Controller Control Register (EL3) when GICv3 is implemented, EL3 is implemented, and FEAT_AA64 is implemented Controls aspects of the behavior of the GIC CPU interface and provides information about the features implemented. GIC control registers Secure GIC ICC_CTLR_EL3 is a 64-bit register. 63 20 63:20 Reserved, RES0. ExtRange 19 19 19 Extended INTID range. 0b0 CPU interface does not support INTIDs in the range 1024..8191. Behavior is UNPREDICTABLE if the IRI delivers an interrupt in the range 1024 to 8191 to the CPU interface. Arm strongly recommends that the IRI is not configured to deliver interrupts in this range to a PE that does not support them. 0b1 CPU interface supports INTIDs in the range 1024..8191 All INTIDs in the range 1024..8191 are treated as requiring deactivation. RO RSS 18 18 18 Range Selector Support. 0b0 Targeted SGIs with affinity level 0 values of 0-15 are supported. 0b1 Targeted SGIs with affinity level 0 values of 0-255 are supported. RO nDS 17 17 17 Disable Security not supported. When a PE implements FEAT_RME and FEAT_SEL2, this field is RAO/WI. 0b0 The CPU interface logic supports disabling of security. 0b1 The CPU interface logic does not support disabling of security, and requires that security is not disabled. RO 16 16 16 Reserved, RES0. A3V 15 15 15 Affinity 3 Valid. If EL3 is present, ICC_CTLR_EL1.A3V is an alias of ICC_CTLR_EL3.A3V 0b0 The CPU interface logic does not support nonzero values of the Aff3 field in SGI generation System registers. 0b1 The CPU interface logic supports nonzero values of the Aff3 field in SGI generation System registers. RO SEIS 14 14 14 SEI Support. Indicates whether the CPU interface supports generation of SEIs: If EL3 is present, ICC_CTLR_EL1.SEIS is an alias of ICC_CTLR_EL3.SEIS 0b0 The CPU interface logic does not support generation of SEIs. 0b1 The CPU interface logic supports generation of SEIs. RO IDbits 13 11 13:11 Identifier bits. Indicates the number of physical interrupt identifier bits supported. All other values are reserved. If EL3 is present, ICC_CTLR_EL1.IDbits is an alias of ICC_CTLR_EL3.IDbits 0b000 16 bits. 0b001 24 bits. RO PRIbits 10 8 10:8 Priority bits. The number of priority bits implemented, minus one. An implementation that supports two Security states must implement at least 32 levels of physical priority (5 priority bits). An implementation that supports only a single Security state must implement at least 16 levels of physical priority (4 priority bits). This field always returns the number of priority bits implemented, regardless of the value of SCR_EL3.NS or the value of GICD_CTLR.DS.The division between group priority and subpriority is defined in the binary point registers ICC_BPR0_EL1 and ICC_BPR1_EL1. This field determines the minimum value of ICC_BPR0_EL1. RO 7 7 7 Reserved, RES0. PMHE 6 6 6 Priority Mask Hint Enable. Software must write ICC_PMR_EL1 to 0xFF before clearing this field to 0. An implementation might choose to make this field RAO/WI if priority-based routing is always used An implementation might choose to make this field RAZ/WI if priority-based routing is never used If EL3 is present, ICC_CTLR_EL1.PMHE is an alias of ICC_CTLR_EL3.PMHE. 0b0 Disables use of the priority mask register as a hint for interrupt distribution. 0b1 Enables use of the priority mask register as a hint for interrupt distribution. '0' RM 5 5 5 Routing Modifier. This bit controls whether EL3 can acknowledge, or observe as the Highest Priority Pending Interrupt, Secure Group 0 and Non-secure Group 1 interrupts. The Routing Modifier bit is supported in AArch64 only. In systems without EL3 the behavior is as if the value is 0. Software must ensure this bit is 0 when the Secure copy of ICC_SRE_EL1.SRE is 1, otherwise system behavior is UNPREDICTABLE. In systems without EL3 or where the Secure copy of ICC_SRE_EL1.SRE is RAO/WI, this bit is RES0. 0b0 Secure Group 0 and Non-secure Group 1 interrupts can be acknowledged and observed as the highest priority interrupt at EL3. 0b1 Secure Group 0 and Non-secure Group 1 interrupts cannot be acknowledged and observed as the highest priority interrupt at EL3. Secure Group 0 interrupts return a special INTID value of 1020. This affects accesses to ICC_IAR0_EL1 and ICC_HPPIR0_EL1. Non-secure Group 1 interrupts return a special INTID value of 1021. This affects accesses to ICC_IAR1_EL1 and ICC_HPPIR1_EL1. AU EOImode_EL1NS 4 4 4 EOI mode for interrupts handled at Non-secure EL1 and EL2. Controls whether a write to an End of Interrupt register also deactivates the interrupt. If EL3 is present, ICC_CTLR_EL1(NS).EOImode is an alias of ICC_CTLR_EL3.EOImode_EL1NS. 0b0 ICC_EOIR0_EL1 and ICC_EOIR1_EL1 provide both priority drop and interrupt deactivation functionality. Accesses to ICC_DIR_EL1 are UNPREDICTABLE. 0b1 ICC_EOIR0_EL1 and ICC_EOIR1_EL1 provide priority drop functionality only. ICC_DIR_EL1 provides interrupt deactivation functionality. AU EOImode_EL1S 3 3 3 EOI mode for interrupts handled at Secure EL1 and EL2. Controls whether a write to an End of Interrupt register also deactivates the interrupt. If EL3 is present, ICC_CTLR_EL1(S).EOImode is an alias of ICC_CTLR_EL3.EOImode_EL1S. 0b0 ICC_EOIR0_EL1 and ICC_EOIR1_EL1 provide both priority drop and interrupt deactivation functionality. Accesses to ICC_DIR_EL1 are UNPREDICTABLE. 0b1 ICC_EOIR0_EL1 and ICC_EOIR1_EL1 provide priority drop functionality only. ICC_DIR_EL1 provides interrupt deactivation functionality. AU EOImode_EL3 2 2 2 EOI mode for interrupts handled at EL3. Controls whether a write to an End of Interrupt register also deactivates the interrupt. 0b0 ICC_EOIR0_EL1 and ICC_EOIR1_EL1 provide both priority drop and interrupt deactivation functionality. Accesses to ICC_DIR_EL1 are UNPREDICTABLE. 0b1 ICC_EOIR0_EL1 and ICC_EOIR1_EL1 provide priority drop functionality only. ICC_DIR_EL1 provides interrupt deactivation functionality. AU CBPR_EL1NS 1 1 1 Common Binary Point Register, EL1 Non-secure. Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1 and EL2. If EL3 is present, ICC_CTLR_EL1(NS).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1NS. 0b0 ICC_BPR0_EL1 determines the preemption group for Group 0 interrupts only. ICC_BPR1_EL1 determines the preemption group for Non-secure Group 1 interrupts. 0b1 ICC_BPR0_EL1 determines the preemption group for Group 0 interrupts and Non-secure Group 1 interrupts. Non-secure accesses to GICC_BPR and ICC_BPR1_EL1 access the state of ICC_BPR0_EL1. AU CBPR_EL1S 0 0 0 Common Binary Point Register, EL1 Secure. Controls whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts at EL1 and EL2. If EL3 is present, ICC_CTLR_EL1(S).CBPR is an alias of ICC_CTLR_EL3.CBPR_EL1S. 0b0 ICC_BPR0_EL1 determines the preemption group for Group 0 interrupts only. ICC_BPR1_EL1 determines the preemption group for Secure Group 1 interrupts. 0b1 ICC_BPR0_EL1 determines the preemption group for Group 0 interrupts and Secure Group 1 interrupts. Secure EL1 and Secure EL2 accesses to ICC_BPR1_EL1 access the state of ICC_BPR0_EL1. AU MRS <Xt>, ICC_CTLR_EL3 if !(IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = ICC_CTLR_EL3(); end; end; MSR ICC_CTLR_EL3, <Xt> if !(IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else ICC_CTLR_EL3() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel