ICC_DIR_EL1 Interrupt Controller Deactivate Interrupt Register when GICv3 is implemented and FEAT_AA64 is implemented ICC_DIR Functional AArch32 31 0 31 0 31 0 31 0 When interrupt priority drop is separated from interrupt deactivation, a write to this register deactivates the specified interrupt. GIC control registers GIC ICC_DIR_EL1 is a 64-bit register. 63 24 63:24 Reserved, RES0. INTID 23 0 23:0 The INTID of the interrupt to be deactivated. This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICC_CTLR_EL1.IDbits and ICC_CTLR_EL3.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0. There are two cases when writing to ICC_DIR_EL1 that were UNPREDICTABLE for a corresponding GICv2 write to GICC_DIR: When EOImode == 0. GICv3 implementations must ignore such writes. In systems supporting system error generation, an implementation might generate an SEI. When EOImode == 1 but no EOI has been issued. The interrupt will be deactivated by the Distributor, however the active priority in the CPU interface for the interrupt will remain set (because no EOI was issued). MSR ICC_DIR_EL1, <Xt> if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TDIR == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().FMO == '1' then ICV_DIR_EL1() = X{64}(t); elsif EL2Enabled() && HCR_EL2().IMO == '1' then ICV_DIR_EL1() = X{64}(t); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ICC_DIR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ICC_DIR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else ICC_DIR_EL1() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel