ICC_EOIR0_EL1 Interrupt Controller End Of Interrupt Register 0 when GICv3 is implemented and FEAT_AA64 is implemented ICC_EOIR0 Functional AArch32 31 0 31 0 31 0 31 0 A PE writes to this register to inform the CPU interface that it has completed the processing of the specified Group 0 interrupt. GIC control registers GIC ICC_EOIR0_EL1 is a 64-bit register. 63 24 63:24 Reserved, RES0. INTID 23 0 23:0 The INTID from the corresponding ICC_IAR0_EL1 access. This field has either 16 or 24 bits implemented. The number of implemented bits can be found in ICC_CTLR_EL1.IDbits and ICC_CTLR_EL3.IDbits. If only 16 bits are implemented, bits [23:16] of this register are RES0. If the EOImode bit for the current Exception level and Security state is 0, a write to this register drops the priority for the interrupt, and also deactivates the interrupt. If the EOImode bit for the current Exception level and Security state is 1, a write to this register only drops the priority for the interrupt. Software must write to ICC_DIR_EL1 to deactivate the interrupt. The EOImode bit for the current Exception level and Security state is determined as follows: If EL3 is not implemented, the appropriate bit is ICC_CTLR_EL1.EOIMode. If EL3 is implemented and the software is executing at EL3, the appropriate bit is ICC_CTLR_EL3.EOImode_EL3. If EL3 is implemented and the software is not executing at EL3, the bit depends on the current Security state: If the software is executing in Secure state, the bit is ICC_CTLR_EL3.EOImode_EL1S. If the software is executing in Non-secure state, the bit is ICC_CTLR_EL3.EOImode_EL1NS. A write to this register must correspond to the most recent valid read by this PE from an Interrupt Acknowledge Register, and must correspond to the INTID that was read from ICC_IAR0_EL1, otherwise the system behavior is UNPREDICTABLE. A valid read is a read that returns a valid INTID that is not a special INTID. A write of a Special INTID is ignored. For more information, see 'Special INTIDs' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). MSR ICC_EOIR0_EL1, <Xt> if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FIQ == '1' then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TALL0 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().FMO == '1' then ICV_EOIR0_EL1() = X{64}(t); elsif HaveEL(EL3) && SCR_EL3().FIQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ICC_EOIR0_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().FIQ == '1' then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().FIQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ICC_EOIR0_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else ICC_EOIR0_EL1() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel