ICC_IGRPEN1_EL1 Interrupt Controller Interrupt Group 1 Enable Register when GICv3 is implemented and FEAT_AA64 is implemented ICC_IGRPEN1 Architectural AArch32 31 0 ICC_IGRPEN1_EL1_S 31 0 ICC_IGRPEN1_S 31 0 31 0 ICC_IGRPEN1 Architectural AArch32 31 0 ICC_IGRPEN1_EL1_NS 31 0 ICC_IGRPEN1_NS 31 0 31 0 Controls whether Group 1 interrupts are enabled for the current Security state. GIC control registers GIC This register is banked between ICC_IGRPEN1_EL1 and ICC_IGRPEN1_EL1_S and ICC_IGRPEN1_EL1_NS. ICC_IGRPEN1_EL1 is a 64-bit register. This register has the following instances: ICC_IGRPEN1_EL1, when EL3 is not implemented. ICC_IGRPEN1_EL1_S, when EL3 is implemented. ICC_IGRPEN1_EL1_NS, when EL3 is implemented. 63 1 63:1 Reserved, RES0. Enable 0 0 0 Enables Group 1 interrupts for the current Security state. Virtual accesses to this register update ICH_VMCR_EL2.VENG1. If EL3 is present: The Secure ICC_IGRPEN1_EL1.Enable bit is a read/write alias of the ICC_IGRPEN1_EL3.EnableGrp1S bit. The Non-secure ICC_IGRPEN1_EL1.Enable bit is a read/write alias of the ICC_IGRPEN1_EL3.EnableGrp1NS bit. If the highest priority pending interrupt for that PE is a Group 1 interrupt using 1 of N model, then the interrupt will target another PE as a result of the Enable bit changing from 1 to 0. 0b0 Group 1 interrupts are disabled for the current Security state. 0b1 Group 1 interrupts are enabled for the current Security state. '0' MRS <Xt>, ICC_IGRPEN1_EL1 if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().IRQ == '1' then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGRTR_EL2().ICC_IGRPENn_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TALL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then X{64}(t) = ICV_IGRPEN1_EL1(); elsif HaveEL(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_IGRPEN1_EL1_S(); else X{64}(t) = ICC_IGRPEN1_EL1_NS(); end; else X{64}(t) = ICC_IGRPEN1_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().IRQ == '1' then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_IGRPEN1_EL1_S(); else X{64}(t) = ICC_IGRPEN1_EL1_NS(); end; else X{64}(t) = ICC_IGRPEN1_EL1(); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_IGRPEN1_EL1_S(); else X{64}(t) = ICC_IGRPEN1_EL1_NS(); end; end; end; MSR ICC_IGRPEN1_EL1, <Xt> if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().IRQ == '1' then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3().FGTEn == '1') && HFGWTR_EL2().ICC_IGRPENn_EL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TALL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then ICV_IGRPEN1_EL1() = X{64}(t); elsif HaveEL(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_IGRPEN1_EL1_S() = X{64}(t); else ICC_IGRPEN1_EL1_NS() = X{64}(t); end; else ICC_IGRPEN1_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().IRQ == '1' then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_IGRPEN1_EL1_S() = X{64}(t); else ICC_IGRPEN1_EL1_NS() = X{64}(t); end; else ICC_IGRPEN1_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else if EffectiveSCR_EL3_NS() == '0' then ICC_IGRPEN1_EL1_S() = X{64}(t); else ICC_IGRPEN1_EL1_NS() = X{64}(t); end; end; end; 2026-03-26 20:27:25 2026-03_rel