ICC_IGRPEN1_EL3 Interrupt Controller Interrupt Group 1 Enable Register (EL3) when GICv3 is implemented, EL3 is implemented, and FEAT_AA64 is implemented Controls whether Group 1 interrupts are enabled or not. GIC control registers GIC ICC_IGRPEN1_EL3 is a 64-bit register. 63 2 63:2 Reserved, RES0. EnableGrp1S 1 1 1 Enables Group 1 interrupts for the Secure state. The Secure ICC_IGRPEN1_EL1.Enable bit is a read/write alias of the ICC_IGRPEN1_EL3.EnableGrp1S bit. If the highest priority pending interrupt for that PE is a Group 1 interrupt using 1 of N model, then the interrupt will target another PE as a result of the Enable bit changing from 1 to 0. 0b0 Secure Group 1 interrupts are disabled. 0b1 Secure Group 1 interrupts are enabled. '0' EnableGrp1NS 0 0 0 Enables Group 1 interrupts for the Non-secure state. The Non-secure ICC_IGRPEN1_EL1.Enable bit is a read/write alias of the ICC_IGRPEN1_EL3.EnableGrp1NS bit. If the highest priority pending interrupt for that PE is a Group 1 interrupt using 1 of N model, then the interrupt will target another PE as a result of the Enable bit changing from 1 to 0. 0b0 Non-secure Group 1 interrupts are disabled. 0b1 Non-secure Group 1 interrupts are enabled. '0' MRS <Xt>, ICC_IGRPEN1_EL3 if !(IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = ICC_IGRPEN1_EL3(); end; end; MSR ICC_IGRPEN1_EL3, <Xt> if !(IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else ICC_IGRPEN1_EL3() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel