ICC_PMR_EL1
Interrupt Controller Interrupt Priority Mask Register
when GICv3 is implemented and FEAT_AA64 is implemented
ICC_PMR
Architectural
AArch32
31
0
31
0
31
0
31
0
Provides an interrupt priority filter. Only interrupts with a higher priority than the value in this register are signaled to the PE.
Writes to this register must be high performance and must ensure that no interrupt of lower priority than the written value occurs after the write, without requiring an ISB or an exception boundary.
GIC control registers
GIC
The effect of writes to ICC_PMR_EL1 are guaranteed to be visible to later instructions in the Execution stream. This ensures that no interrupts below the written PMR value will be taken after a write to this register is architecturally executed. For more information, see 'Observability of the effects of accesses to the GIC registers' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).
ICC_PMR_EL1 is a 64-bit register.
63
8
63:8
Reserved, RES0.
Priority
7
0
7:0
The priority mask level for the CPU interface. If the priority of an interrupt is higher than the value indicated by this field, the interface signals the interrupt to the PE.
The possible priority field values are as follows:
Implemented priority bitsPossible priority field valuesNumber of priority levels
[7:0]0x00-0xFF (0-255), all values256
[7:1]0x00-0xFE (0-254), even values only128
[7:2]0x00-0xFC (0-252), in steps of 464
[7:3]0x00-0xF8 (0-248), in steps of 832
[7:4]0x00-0xF0 (0-240), in steps of 1616
Unimplemented priority bits are RAZ/WI.
0x00
MRS <Xt>, ICC_PMR_EL1
if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then
Undefined();
elsif ICC_SRE_EL1().SRE == '0' then
AArch64_SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && ICH_HCR_EL2().TC == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && HCR_EL2().FMO == '1' then
X{64}(t) = ICV_PMR_EL1();
elsif EL2Enabled() && HCR_EL2().IMO == '1' then
X{64}(t) = ICV_PMR_EL1();
elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
X{64}(t) = ICC_PMR_EL1();
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then
Undefined();
elsif ICC_SRE_EL2().SRE == '0' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
X{64}(t) = ICC_PMR_EL1();
end;
elsif PSTATE.EL == EL3 then
if ICC_SRE_EL3().SRE == '0' then
AArch64_SystemAccessTrap(EL3, 0x18);
else
X{64}(t) = ICC_PMR_EL1();
end;
end;
MSR ICC_PMR_EL1, <Xt>
if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then
Undefined();
elsif PSTATE.EL == EL0 then
Undefined();
elsif PSTATE.EL == EL1 then
if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then
Undefined();
elsif ICC_SRE_EL1().SRE == '0' then
AArch64_SystemAccessTrap(EL1, 0x18);
elsif EL2Enabled() && ICH_HCR_EL2().TC == '1' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif EL2Enabled() && HCR_EL2().FMO == '1' then
ICV_PMR_EL1() = X{64}(t);
elsif EL2Enabled() && HCR_EL2().IMO == '1' then
ICV_PMR_EL1() = X{64}(t);
elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
ICC_PMR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL2 then
if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then
Undefined();
elsif ICC_SRE_EL2().SRE == '0' then
AArch64_SystemAccessTrap(EL2, 0x18);
elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then
if EL3SDDUndef() then
Undefined();
else
AArch64_SystemAccessTrap(EL3, 0x18);
end;
else
ICC_PMR_EL1() = X{64}(t);
end;
elsif PSTATE.EL == EL3 then
if ICC_SRE_EL3().SRE == '0' then
AArch64_SystemAccessTrap(EL3, 0x18);
else
ICC_PMR_EL1() = X{64}(t);
end;
end;
2026-03-26 20:27:25
2026-03_rel