ICC_RPR_EL1 Interrupt Controller Running Priority Register when GICv3 is implemented and FEAT_AA64 is implemented ICC_RPR Functional AArch32 31 0 31 0 31 0 31 0 Indicates the Running priority of the CPU interface. GIC control registers GIC ICC_RPR_EL1 is a 64-bit register. NMI 63 63 0 Indicates whether the running priority is from a NMI. 0b0 When GICD_CTLR.DS==1, there are no Active NMIs, or all Active NMIs have undergone priority drop. When GICD_CTLR.DS==0: For Non-secure and Realm reads, there are no Active Non-secure Group 1 NMIs, or all Active Non-secure Group 1 NMIs have undergone priority drop. For Secure and Root reads, there are no Active Secure Group 1 NMIs, or all Active Secure Group 1 NMIs have undergone priority drop. 0b1 When GICD_CTLR.DS==1, there is an Active NMI. When GICD_CTLR.DS==0: For Non-secure and Realm reads, there is an Active Non-secure Group 1 NMI. For Secure and Root reads, there is an Active Secure Group 1 NMI. When FEAT_GICv3_NMI is implemented 63 63 63 Reserved, RES0. Otherwise NMI_NS 62 62 0 Indicates whether the running priority is from a Non-secure Group 1 NMI. For Non-secure and Realm accesses, this field is RES0. 0b0 There are no Active Non-secure Group 1 NMIs, or all Active Non-secure Group 1 NMIs have undergone priority drop. 0b1 There is an Active Non-secure Group 1 NMI which has not undergone priority drop. When FEAT_GICv3_NMI is implemented and EL3 is implemented 62 62 62 Reserved, RES0. Otherwise 61 8 61:8 Reserved, RES0. Priority 7 0 7:0 The current running priority on the CPU interface. This is the group priority of the current active interrupt. The group priority of a Secure NMI, or NMI when GICD_CTLR.DS is 1, is 0x00. The group priority of a Non-secure NMI is 0x80, saturated to 0x00 for Non-secure reads. If there are no active interrupts on the CPU interface, or all active interrupts have undergone a priority drop, the value returned is the Idle priority. The priority returned is the group priority as if the BPR for the current Exception level and Security state was set to the minimum value of BPR for the number of implemented priority bits. If 8 bits of priority are implemented the group priority is bits[7:1] of the priority. Software cannot determine the number of implemented priority bits from a read of this register. MRS <Xt>, ICC_RPR_EL1 if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().FMO == '1' then X{64}(t) = ICV_RPR_EL1(); elsif EL2Enabled() && HCR_EL2().IMO == '1' then X{64}(t) = ICV_RPR_EL1(); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ICC_RPR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else X{64}(t) = ICC_RPR_EL1(); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = ICC_RPR_EL1(); end; end; 2026-03-26 20:27:25 2026-03_rel