ICC_SGI1R_EL1 Interrupt Controller Software Generated Interrupt Group 1 Register when GICv3 is implemented and FEAT_AA64 is implemented ICC_SGI1R Functional AArch32 Generates Group 1 SGIs for the current Security state. GIC control registers GIC Under certain conditions a write to ICC_SGI1R_EL1 can generate Group 0 interrupts, see 'Forwarding an SGI to a target PE' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). ICC_SGI1R_EL1 is a 64-bit register. 63 56 63:56 Reserved, RES0. Aff3 55 48 55:48 The affinity 3 value of the affinity path of the cluster for which SGI interrupts will be generated. If the IRM bit is 1, this field is RES0. RS 47 44 47:44 RangeSelector Controls which group of 16 values is represented by the TargetList field. TargetList[n] represents aff0 value ((RS * 16) + n). When ICC_CTLR_EL1.RSS==0, RS is RES0. When ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0, writing this register with RS != 0 is a CONSTRAINED UNPREDICTABLE choice of: The write is ignored. The RS field is treated as 0. 43 41 43:41 Reserved, RES0. IRM 40 40 40 Interrupt Routing Mode. Determines how the generated interrupts are distributed to PEs. Possible values are: 0b0 Interrupts routed to the PEs specified by Aff3.Aff2.Aff1.<target list>. 0b1 Interrupts routed to all PEs in the system, excluding "self". Aff2 39 32 39:32 The affinity 2 value of the affinity path of the cluster for which SGI interrupts will be generated. If the IRM bit is 1, this field is RES0. 31 28 31:28 Reserved, RES0. INTID 27 24 27:24 The INTID of the SGI. Aff1 23 16 23:16 The affinity 1 value of the affinity path of the cluster for which SGI interrupts will be generated. If the IRM bit is 1, this field is RES0. TargetList 15 0 15:0 Target List. The set of PEs for which SGI interrupts will be generated. Each bit corresponds to the PE within a cluster with an Affinity 0 value equal to the bit number. If SRE is set only for EL3, software executing at EL3 might use the System register interface to generate SGIs. Therefore, the Distributor must always be able to receive and acknowledge Generate SGI packets received from CPU interface regardless of the ARE settings for a Security state. However, the Distributor might discard such packets.If the IRM bit is 1, this field is RES0. If a bit is 1 and the bit does not correspond to a valid target PE, the bit must be ignored by the Distributor. It is IMPLEMENTATION DEFINED whether, in such cases, a Distributor can signal a system error. Accesses at EL3 are treated as Secure regardless of the value of SCR_EL3.NS. MSR ICC_SGI1R_EL1, <Xt> if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().FMO == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ICC_SGI1R_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; else ICC_SGI1R_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else ICC_SGI1R_EL1() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel