ICC_SRE_EL1 Interrupt Controller System Register Enable Register (EL1) when GICv3 is implemented and FEAT_AA64 is implemented ICC_SRE Architectural AArch32 31 0 ICC_SRE_EL1_S 31 0 ICC_SRE_S 31 0 31 0 ICC_SRE Architectural AArch32 31 0 ICC_SRE_EL1_NS 31 0 ICC_SRE_NS 31 0 31 0 ICC_SRE Architectural AArch32 31 0 31 0 Controls whether the System register interface or the memory-mapped interface to the GIC CPU interface is used for EL1. GIC control registers GIC This register is banked between ICC_SRE_EL1 and ICC_SRE_EL1_S and ICC_SRE_EL1_NS. ICC_SRE_EL1 is a 64-bit register. This register has the following instances: ICC_SRE_EL1, when EL3 is not implemented. ICC_SRE_EL1_S, when EL3 is implemented. ICC_SRE_EL1_NS, when EL3 is implemented. 63 3 63:3 Reserved, RES0. DIB 2 2 2 Disable IRQ bypass. If EL3 is implemented and GICD_CTLR.DS == 0, this field is a read-only alias of ICC_SRE_EL3.DIB. If EL3 is implemented and GICD_CTLR.DS == 1, and EL2 is not implemented, this field is a read/write alias of ICC_SRE_EL3.DIB. If EL3 is not implemented and EL2 is implemented, this field is a read-only alias of ICC_SRE_EL2.DIB. If GICD_CTLR.DS == 1 and EL2 is implemented, this field is a read-only alias of ICC_SRE_EL2.DIB. In systems that do not support IRQ bypass, this field is RAO/WI. 0b0 IRQ bypass enabled. 0b1 IRQ bypass disabled. '0' DFB 1 1 1 Disable FIQ bypass. If EL3 is implemented and GICD_CTLR.DS == 0, this field is a read-only alias of ICC_SRE_EL3.DFB. If EL3 is implemented and GICD_CTLR.DS == 1, and EL2 is not implemented, this field is a read/write alias of ICC_SRE_EL3.DFB. If EL3 is not implemented and EL2 is implemented, this field is a read-only alias of ICC_SRE_EL2.DFB. If GICD_CTLR.DS == 1 and EL2 is implemented, this field is a read-only alias of ICC_SRE_EL2.DFB. In systems that do not support FIQ bypass, this field is RAO/WI. 0b0 FIQ bypass enabled. 0b1 FIQ bypass disabled. '0' SRE 0 0 0 System Register Enable. If software changes this bit from 1 to 0 in the Secure instance of this register, the results are UNPREDICTABLE. If an implementation supports only a System register interface to the GIC CPU interface, this bit is RAO/WI. If EL3 is implemented and ICC_SRE_EL3.SRE==0 the Secure copy of this bit is RAZ/WI. If ICC_SRE_EL3.SRE is changed from zero to one, the Secure copy of this bit becomes UNKNOWN. If EL2 is implemented and ICC_SRE_EL2.SRE==0 the Non-secure copy of this bit is RAZ/WI. If ICC_SRE_EL2.SRE is changed from zero to one, the Non-secure copy of this bit becomes UNKNOWN. If EL3 is implemented and ICC_SRE_EL3.SRE==0 the Non-secure copy of this bit is RAZ/WI. If ICC_SRE_EL3.SRE is changed from zero to one, the Non-secure copy of this bit becomes UNKNOWN. If Realm Management Extension is implemented, this field is RAO/WI. GICv3 implementations that do not require GICv2 compatibility might choose to make this bit RAO/WI. The following options are supported: The Non-secure copy of ICC_SRE_EL1.SRE can be RAO/WI if ICC_SRE_EL2.SRE is also RAO/WI. This means all Non-secure software, including VMs using only virtual interrupts, must access the GIC using System registers. The Secure copy of ICC_SRE_EL1.SRE can be RAO/WI if ICC_SRE_EL3.SRE and ICC_SRE_EL2.SRE are also RAO/WI. This means that all Secure software must access the GIC using System registers and all Non-secure accesses to registers for physical interrupts must use System registers. A VM using only virtual interrupts might still use memory-mapped access if the Non-secure copy of ICC_SRE_EL1.SRE is not RAO/WI. 0b0 The memory-mapped interface must be used. Access at EL1 to any ICC_* System register other than ICC_SRE_EL1 is trapped to EL1. 0b1 The System register interface for the current Security state is enabled. '0' Execution with ICC_SRE_EL1.SRE set to 0 might make some System registers UNKNOWN. MRS <Xt>, ICC_SRE_EL1 if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && EffectiveICC_SRE_EL3_Enable() == '0' then Undefined(); elsif EL2Enabled() && EffectiveICC_SRE_EL2_Enable() == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && EffectiveICC_SRE_EL3_Enable() == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_SRE_EL1_S(); else X{64}(t) = ICC_SRE_EL1_NS(); end; else X{64}(t) = ICC_SRE_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && EffectiveICC_SRE_EL3_Enable() == '0' then Undefined(); elsif HaveEL(EL3) && EffectiveICC_SRE_EL3_Enable() == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_SRE_EL1_S(); else X{64}(t) = ICC_SRE_EL1_NS(); end; else X{64}(t) = ICC_SRE_EL1(); end; elsif PSTATE.EL == EL3 then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_SRE_EL1_S(); else X{64}(t) = ICC_SRE_EL1_NS(); end; end; MSR ICC_SRE_EL1, <Xt> if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && EffectiveICC_SRE_EL3_Enable() == '0' then Undefined(); elsif EL2Enabled() && EffectiveICC_SRE_EL2_Enable() == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && EffectiveICC_SRE_EL3_Enable() == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_SRE_EL1_S() = X{64}(t); else ICC_SRE_EL1_NS() = X{64}(t); end; else ICC_SRE_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && EffectiveICC_SRE_EL3_Enable() == '0' then Undefined(); elsif HaveEL(EL3) && EffectiveICC_SRE_EL3_Enable() == '0' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_SRE_EL1_S() = X{64}(t); else ICC_SRE_EL1_NS() = X{64}(t); end; else ICC_SRE_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if EffectiveSCR_EL3_NS() == '0' then ICC_SRE_EL1_S() = X{64}(t); else ICC_SRE_EL1_NS() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel