ICC_SRE_EL3 Interrupt Controller System Register Enable Register (EL3) when GICv3 is implemented, EL3 is implemented, and FEAT_AA64 is implemented Controls whether the System register interface or the memory-mapped interface to the GIC CPU interface is used for EL3. GIC control registers Secure GIC ICC_SRE_EL3 is a 64-bit register. 63 4 63:4 Reserved, RES0. Enable 3 3 3 Enable. Enables lower Exception level access to ICC_SRE_EL1 and ICC_SRE_EL2. If ICC_SRE_EL3.SRE is RAO/WI, an implementation is permitted to make the Enable bit RAO/WI. If ICC_SRE_EL3.SRE is 0, the Enable bit behaves as 1 for all purposes other than reading the value of the bit. 0b0 EL1 accesses to ICC_SRE_EL1 trap to EL3, unless these accesses are trapped to EL2 as a result of ICC_SRE_EL2.Enable == 0. EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 trap to EL3. 0b1 EL1 accesses to ICC_SRE_EL1 do not trap to EL3. EL2 accesses to ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3. AU DIB 2 2 2 Disable IRQ bypass. In systems that do not support IRQ bypass, this bit is RAO/WI. 0b0 IRQ bypass enabled. 0b1 IRQ bypass disabled. '0' DFB 1 1 1 Disable FIQ bypass. In systems that do not support FIQ bypass, this bit is RAO/WI. 0b0 FIQ bypass enabled. 0b1 FIQ bypass disabled. '0' SRE 0 0 0 System Register Enable. If software changes this bit from 1 to 0, the results are UNPREDICTABLE. If Realm Management Extension is implemented, this field is RAO/WI. FEAT_GICv3 implementations that do not require GICv2 compatibility might choose to make this bit RAO/WI. 0b0 The memory-mapped interface must be used. Access at EL3 to any ICH_* or ICC_* register other than ICC_SRE_EL1, ICC_SRE_EL2, or ICC_SRE_EL3 is trapped to EL3 0b1 The System register interface to the ICH_* registers and the EL1, EL2, and EL3 ICC_* registers is enabled for EL3. '0' This register is always System register accessible. MRS <Xt>, ICC_SRE_EL3 if !(IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then X{64}(t) = ICC_SRE_EL3(); end; MSR ICC_SRE_EL3, <Xt> if !(IsFeatureImplemented(FEAT_GICv3) && HaveEL(EL3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then Undefined(); elsif PSTATE.EL == EL2 then Undefined(); elsif PSTATE.EL == EL3 then ICC_SRE_EL3() = X{64}(t); end; 2026-03-26 20:27:25 2026-03_rel