ICH_AP1R<n>_EL2 Interrupt Controller Hyp Active Priorities Group 1 Registers when GICv3 is implemented, (EL2 is implemented or EL3 is implemented), and FEAT_AA64 is implemented 0 3 ICH_AP1R<n> Architectural AArch32 31 0 31 0 31 0 31 0 Provides information about Group 1 virtual active priorities for EL2. GIC GIC Host Interface Control Registers Virt If EL2 is not implemented, this register is RES0 from EL3. This register has no effect if EL2 is not enabled in the current Security state. ICH_AP1R<n>_EL2 is a 64-bit register. NMI 63 63 0 Indicates whether the running virtual priority is from a NMI. 0b0 There is no active Group 1 NMI, or all active Group 1 NMIs have undergone priority drop. 0b1 There is an active Group 1 NMI. '0' When FEAT_GICv3_NMI is implemented and n == 0 63 63 63 Reserved, RES0. Otherwise 62 32 62:32 Reserved, RES0. P<x> 31 0 31:0 Group 1 interrupt active priorities. Possible values of each bit are: The correspondence between priority levels and bits depends on the number of bits of priority that are implemented. If 5 bits of preemption are implemented (bits [7:3] of priority), then there are 32 preemption levels, and the active state of these preemption levels are held in ICH_AP1R0_EL2 in the bits corresponding to Priority[7:3]. If 6 bits of preemption are implemented (bits [7:2] of priority), then there are 64 preemption levels, and: The active state of preemption levels 0 - 124 are held in ICH_AP1R0_EL2 in the bits corresponding to 0:Priority[6:2]. The active state of preemption levels 128 - 252 are held in ICH_AP1R1_EL2 in the bits corresponding to 1:Priority[6:2]. If 7 bits of preemption are implemented (bits [7:1] of priority), then there are 128 preemption levels, and: The active state of preemption levels 0 - 62 are held in ICH_AP1R0_EL2 in the bits corresponding to 00:Priority[5:1]. The active state of preemption levels 64 - 126 are held in ICH_AP1R1_EL2 in the bits corresponding to 01:Priority[5:1]. The active state of preemption levels 128 - 190 are held in ICH_AP1R2_EL2 in the bits corresponding to 10:Priority[5:1]. The active state of preemption levels 192 - 254 are held in ICH_AP1R3_EL2 in the bits corresponding to 11:Priority[5:1]. Having the bit corresponding to a priority set to 1 in both ICH_AP0R<n>_EL2 and ICH_AP1R<n>_EL2 might result in UNPREDICTABLE behavior of the interrupt prioritization system for virtual interrupts. 31 0 0b0 There is no Group 1 interrupt active with this priority level, or all active Group 1 interrupts with this priority level have undergone priority-drop. 0b1 There is a Group 1 interrupt active with this priority level which has not undergone priority drop. 0x00000000 If FEAT_GICv3 is implemented, this register is always used for legacy VMs, regardless of the group of the virtual interrupt. Reads and writes to GICV_APR<n> access ICH_AP1R<n>_EL2. For more information about support for legacy VMs, see 'Support for legacy operation of VMs' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069). ICH_AP1R1_EL2 is implemented only in implementations that support 6 or more bits of preemption. ICH_AP1R2_EL2 and ICH_AP1R3_EL2 are implemented only in implementations that support 7 bits of preemption. Unimplemented registers are UNDEFINED. The number of bits of preemption is indicated by ICH_VTR_EL2.PREbits Writing to these registers with any value other than the last read value of the register (or 0x00000000 for a newly set up virtual machine) can result in UNPREDICTABLE behavior of the virtual interrupt prioritization system allowing either: Virtual interrupts that should preempt execution to not preempt execution. Interrupts that should not preempt execution to preempt execution at EL1 or EL0. Writing to the active priority registers in any order other than the following order will result in UNPREDICTABLE behavior: ICH_AP0R<n>_EL2. ICH_AP1R<n>_EL2. 0-3 MRS <Xt>, ICH_AP1R<m>_EL2 let m:integer = UInt(op2[1:0]); if !(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif m == 1 && NUM_GIC_PREEMPTION_BITS < 6 then Undefined(); elsif (m == 2 || m == 3) && NUM_GIC_PREEMPTION_BITS < 7 then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && IsFeatureImplemented(FEAT_GICv3) then X{64}(t) = NVMem(0x4A0 + (8 * m)); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && IsFeatureImplemented(FEAT_GICv3) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = ICH_AP1R_EL2(m); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = ICH_AP1R_EL2(m); end; end; 0-3 MSR ICH_AP1R<m>_EL2, <Xt> let m:integer = UInt(op2[1:0]); if !(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif m == 1 && NUM_GIC_PREEMPTION_BITS < 6 then Undefined(); elsif (m == 2 || m == 3) && NUM_GIC_PREEMPTION_BITS < 7 then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && IsFeatureImplemented(FEAT_GICv3) then NVMem(0x4A0 + (8 * m)) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && IsFeatureImplemented(FEAT_GICv3) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else ICH_AP1R_EL2(m) = X{64}(t); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else ICH_AP1R_EL2(m) = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel