ICH_LR<n>_EL2 Interrupt Controller List Registers when GICv3 is implemented, (EL2 is implemented or EL3 is implemented), and FEAT_AA64 is implemented 0 15 ICH_LR<n> Architectural AArch32 31 0 31 0 31 0 31 0 ICH_LRC<n> Architectural AArch32 63 32 31 0 63 32 31 0 Provides interrupt context information for the virtual CPU interface. GIC GIC Host Interface Control Registers Virt If EL2 is not implemented, this register is RES0 from EL3. If list register n is not implemented, then accesses to this register are UNDEFINED. ICH_LR<n>_EL2 is a 64-bit register. State 63 62 63:62 The state of the interrupt: The GIC updates these state bits as virtual interrupts proceed through the interrupt life cycle. When a virtual interrupt from a List register is acknowledged, the state is updated to the active state regardless of the interrupt type. Entries in the invalid state are ignored, except for the purpose of generating virtual maintenance interrupts. For hardware interrupts, the pending and active state is held in the physical Distributor rather than the virtual CPU interface. A hypervisor must only use the pending and active state for software originated interrupts, which are typically associated with virtual devices, or SGIs. 0b00 Invalid (Inactive). 0b01 Pending. 0b10 Active. 0b11 Pending and active. AU HW 61 61 61 Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt. Deactivation of the virtual interrupt also causes the deactivation of the physical interrupt with the ID that the pINTID field indicates. 0b0 The interrupt is triggered entirely by software. No notification is sent to the Distributor when the virtual interrupt is deactivated. 0b1 The interrupt maps directly to a hardware interrupt. A deactivate interrupt request is sent to the Distributor when the virtual interrupt is deactivated, using the pINTID field from this register to indicate the physical interrupt ID. If ICH_VMCR_EL2.VEOIM is 0, this request corresponds to a write to ICC_EOIR0_EL1 or ICC_EOIR1_EL1. Otherwise, it corresponds to a write to ICC_DIR_EL1. AU Group 60 60 60 Indicates the group for this virtual interrupt. 0b0 This is a Group 0 virtual interrupt. ICH_VMCR_EL2.VFIQEn determines whether it is signaled as a virtual IRQ or as a virtual FIQ, and ICH_VMCR_EL2.VENG0 enables signaling of this interrupt to the virtual machine. 0b1 This is a Group 1 virtual interrupt, signaled as a virtual IRQ. ICH_VMCR_EL2.VENG1 enables the signaling of this interrupt to the virtual machine. If ICH_VMCR_EL2.VCBPR is 0, then ICC_BPR1_EL1 determines if a pending Group 1 interrupt has sufficient priority to preempt current execution. Otherwise, ICH_LR<n>_EL2 determines preemption. AU NMI 59 59 0 Indicates whether the virtual priority has the non-maskable property. Setting ICH_LR<n>_EL2.NMI to 1 when ICH_LR<n>_EL2.State is not Invalid is CONSTRAINTED UNPREDICTABLE if either ICH_LR<n>_EL2.vINTID indicates an LPI or ICH_LR<n>_EL2.Group is 0. The permitted behaviors are: ICH_LR<n>_EL2.NMI is treated as 0 for all purposes other than a direct read of the register. The virtual interrupt is presented with superpriority. 0b0 vINTID does not have the non-maskable interrupt property. 0b1 vINTID has the non-maskable interrupt property. AU When FEAT_GICv3_NMI is implemented 59 59 59 Reserved, RES0. Otherwise 58 56 58:56 Reserved, RES0. Priority 55 48 55:48 The priority of this interrupt. It is IMPLEMENTATION DEFINED how many bits of priority are implemented, though at least five bits must be implemented. Unimplemented bits are RES0 and start from bit[48] up to bit[50]. The number of implemented bits can be discovered from ICH_VTR_EL2.PRIbits. When ICH_LR<n>_EL2.NMI is set to 1, this field is RES0 and the virtual interrupt's priority is treated as 0x00. AU 47 45 47:45 Reserved, RES0. pINTID 44 32 44:32 Physical INTID, for hardware interrupts. When ICH_LR<n>_EL2.HW is 0 (there is no corresponding physical interrupt), this field has the following meaning: Bits[44:42]: RES0. Bit[41]: EOI. If this bit is 1, then when the interrupt identified by vINTID is deactivated, a maintenance interrupt is asserted. Bits[40:32]: RES0. When ICH_LR<n>_EL2.HW is 1 (there is a corresponding physical interrupt): This field indicates the physical INTID. This field is only required to implement enough bits to hold a valid value for the implemented INTID size. Any unused higher order bits are RES0. When ICC_CTLR_EL1.ExtRange is 0, then bits[44:42] of this field are RES0. If the value of pINTID is not a valid INTID, behavior is UNPREDICTABLE. If the value of pINTID indicates a PPI, this field applies to the PPI associated with this same physical PE ID as the virtual CPU interface requesting the deactivation. A hardware physical identifier is only required in List Registers for interrupts that require deactivation. This means only 13 bits of Physical INTID are required, regardless of the number specified by ICC_CTLR_EL1.IDbits. AU vINTID 31 0 31:0 Virtual INTID of the interrupt. If the value of vINTID is 1020-1023 and ICH_LR<n>_EL2.State!=0b00 (Inactive), behavior is UNPREDICTABLE. Behavior is UNPREDICTABLE if two or more List Registers specify the same vINTID when: ICH_LR<n>_EL2.State == 0b01. ICH_LR<n>_EL2.State == 0b10. ICH_LR<n>_EL2.State == 0b11. It is IMPLEMENTATION DEFINED how many bits are implemented, though at least 16 bits must be implemented. Unimplemented bits are RES0. The number of implemented bits can be discovered from ICH_VTR_EL2.IDbits. When ICC_SRE_EL1.SRE == 0, specifying a vINTID in the LPI range is UNPREDICTABLE When a VM is using memory-mapped access to the GIC, software must ensure that the correct source PE ID is provided in bits[12:10]. AU 0-15 MRS <Xt>, ICH_LR<m>_EL2 let m:integer = UInt(CRm[0] :: op2[2:0]); if !(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif m >= NUM_GIC_LIST_REGS then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && IsFeatureImplemented(FEAT_GICv3) then X{64}(t) = NVMem(0x400 + (8 * m)); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && IsFeatureImplemented(FEAT_GICv3) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = ICH_LR_EL2(m); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = ICH_LR_EL2(m); end; end; 0-15 MSR ICH_LR<m>_EL2, <Xt> let m:integer = UInt(CRm[0] :: op2[2:0]); if !(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif m >= NUM_GIC_LIST_REGS then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} && IsFeatureImplemented(FEAT_GICv3) then NVMem(0x400 + (8 * m)) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} && IsFeatureImplemented(FEAT_GICv3) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else ICH_LR_EL2(m) = X{64}(t); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else ICH_LR_EL2(m) = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel