ICH_MISR_EL2 Interrupt Controller Maintenance Interrupt State Register when GICv3 is implemented, (EL2 is implemented or EL3 is implemented), and FEAT_AA64 is implemented ICH_MISR Architectural AArch32 31 0 31 0 31 0 31 0 Indicates which maintenance interrupts are asserted. GIC GIC Host Interface Control Registers Virt If EL2 is not implemented, this register is RES0 from EL3. ICH_MISR_EL2 is a 64-bit register. 63 8 63:8 Reserved, RES0. VGrp1D 7 7 7 vPE Group 1 Disabled. This maintenance interrupt is asserted when ICH_HCR_EL2.VGrp1DIE==1 and ICH_VMCR_EL2.VENG1==is 0. 0b0 vPE Group 1 Disabled maintenance interrupt not asserted. 0b1 vPE Group 1 Disabled maintenance interrupt asserted. '0' VGrp1E 6 6 6 vPE Group 1 Enabled. This maintenance interrupt is asserted when ICH_HCR_EL2.VGrp1EIE==1 and ICH_VMCR_EL2.VENG1==is 1. 0b0 vPE Group 1 Enabled maintenance interrupt not asserted. 0b1 vPE Group 1 Enabled maintenance interrupt asserted. '0' VGrp0D 5 5 5 vPE Group 0 Disabled. This maintenance interrupt is asserted when ICH_HCR_EL2.VGrp0DIE==1 and ICH_VMCR_EL2.VENG0==0. 0b0 vPE Group 0 Disabled maintenance interrupt not asserted. 0b1 vPE Group 0 Disabled maintenance interrupt asserted. '0' VGrp0E 4 4 4 vPE Group 0 Enabled. This maintenance interrupt is asserted when ICH_HCR_EL2.VGrp0EIE==1 and ICH_VMCR_EL2.VENG0==1. 0b0 vPE Group 0 Enabled maintenance interrupt not asserted. 0b1 vPE Group 0 Enabled maintenance interrupt asserted. '0' NP 3 3 3 No Pending. This maintenance interrupt is asserted when ICH_HCR_EL2.NPIE==1 and no List register is in pending state. 0b0 No Pending maintenance interrupt not asserted. 0b1 No Pending maintenance interrupt asserted. '0' LRENP 2 2 2 List Register Entry Not Present. This maintenance interrupt is asserted when ICH_HCR_EL2.LRENPIE==1 and ICH_HCR_EL2.EOIcount is nonzero. 0b0 List Register Entry Not Present maintenance interrupt not asserted. 0b1 List Register Entry Not Present maintenance interrupt asserted. '0' U 1 1 1 Underflow. This maintenance interrupt is asserted when ICH_HCR_EL2.UIE==1 and zero or one of the List register entries are marked as a valid interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits do not equal 0x0. 0b0 Underflow maintenance interrupt not asserted. 0b1 Underflow maintenance interrupt asserted. '0' EOI 0 0 0 End Of Interrupt. This maintenance interrupt is asserted when at least one bit in ICH_EISR_EL2 is 1. 0b0 End Of Interrupt maintenance interrupt not asserted. 0b1 End Of Interrupt maintenance interrupt asserted. '0' The U and NP bits do not include the status of any pending/active 'VSet (IRI)' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069) packets because these bits control generation of interrupts that allow software management of the contents of the List Registers (which are not affected by 'VSet (IRI)' packets). MRS <Xt>, ICH_MISR_EL2 if !(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} && IsFeatureImplemented(FEAT_GICv3) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = ICH_MISR_EL2(); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = ICH_MISR_EL2(); end; end; 2026-03-26 20:27:25 2026-03_rel