ICH_VMCR_EL2 Interrupt Controller Virtual Machine Control Register when GICv3 is implemented, (EL2 is implemented or EL3 is implemented), and FEAT_AA64 is implemented ICH_VMCR Architectural AArch32 31 0 31 0 31 0 31 0 Enables the hypervisor to save and restore the virtual machine view of the GIC state. GIC GIC Host Interface Control Registers Virt If EL2 is not implemented, this register is RES0 from EL3. This register has no effect if EL2 is not enabled in the current Security state. ICH_VMCR_EL2 is a 64-bit register. 63 32 63:32 Reserved, RES0. VPMR 31 24 31:24 Virtual Priority Mask. The priority mask level for the virtual CPU interface. If the priority of a pending virtual interrupt is higher than the value indicated by this field, the interface signals the virtual interrupt to the PE. This field is an alias of ICV_PMR_EL1.Priority. VBPR0 23 21 23:21 Virtual Binary Point Register, Group 0. Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 0 interrupt preemption, and also determines Group 1 interrupt preemption if ICH_VMCR_EL2.VCBPR == 1. This field is an alias of ICV_BPR0_EL1.BinaryPoint. The minimum value of this field is determined by ICH_VTR_EL2.PREbits. An attempt to program the binary point field to a value less than the minimum value sets the field to the minimum value. VBPR1 20 18 20:18 Virtual Binary Point Register, Group 1. Defines the point at which the priority value fields split into two parts, the group priority field and the subpriority field. The group priority field determines Group 1 interrupt preemption if ICH_VMCR_EL2.VCBPR == 0. This field is an alias of ICV_BPR1_EL1.BinaryPoint. This field is always accessible to EL2 accesses, regardless of the setting of the ICH_VMCR_EL2.VCBPR field. For Non-secure writes, the minimum value of this field is the minimum value of ICH_VMCR_EL2.VBPR0 plus one. For Secure writes, the minimum value of this field is the minimum value of ICH_VMCR_EL2.VBPR0. An attempt to program the binary point field to a value less than the minimum value sets the field to the minimum value. 17 10 17:10 Reserved, RES0. VEOIM 9 9 9 Virtual EOI mode. Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt: This bit is an alias of ICV_CTLR_EL1.EOImode. 0b0 ICV_EOIR0_EL1 and ICV_EOIR1_EL1 provide both priority drop and interrupt deactivation functionality. Accesses to ICV_DIR_EL1 are UNPREDICTABLE. 0b1 ICV_EOIR0_EL1 and ICV_EOIR1_EL1 provide priority drop functionality only. ICV_DIR_EL1 provides interrupt deactivation functionality. 8 5 8:5 Reserved, RES0. VCBPR 4 4 4 Virtual Common Binary Point Register. Possible values of this bit are: This field is an alias of ICV_CTLR_EL1.CBPR. 0b0 ICV_BPR1_EL1 determines the preemption group for virtual Group 1 interrupts. 0b1 ICV_BPR0_EL1 determines the preemption group for virtual Group 1 interrupts. VFIQEn 3 3 3 Virtual FIQ enable. Possible values of this bit are: This bit is an alias of GICV_CTLR.FIQEn. In implementations where the Non-secure copy of ICC_SRE_EL1.SRE is always 1, this bit is RES1. 0b0 Group 0 virtual interrupts are presented as virtual IRQs. 0b1 Group 0 virtual interrupts are presented as virtual FIQs. VAckCtl 2 2 2 Virtual AckCtl. Possible values of this bit are: This bit is an alias of GICV_CTLR.AckCtl. This field is supported for backward compatibility with GICv2. Arm deprecates the use of this field. In implementations where the Non-secure copy of ICC_SRE_EL1.SRE is always 1, this bit is RES0. 0b0 If the highest priority pending interrupt is Group 1, a read of GICV_IAR or GICV_HPPIR returns an INTID of 1022. 0b1 If the highest priority pending interrupt is Group 1, a read of GICV_IAR or GICV_HPPIR returns the INTID of the corresponding interrupt. VENG1 1 1 1 Virtual Group 1 interrupt enable. Possible values of this bit are: This bit is an alias of ICV_IGRPEN1_EL1.Enable. 0b0 Virtual Group 1 interrupts are disabled. 0b1 Virtual Group 1 interrupts are enabled. VENG0 0 0 0 Virtual Group 0 interrupt enable. Possible values of this bit are: This bit is an alias of ICV_IGRPEN0_EL1.Enable. 0b0 Virtual Group 0 interrupts are disabled. 0b1 Virtual Group 0 interrupts are enabled. When EL2 is using System register access, EL1 using either System register or memory-mapped access must be supported. MRS <Xt>, ICH_VMCR_EL2 if !(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then X{64}(t) = NVMem(0x4C8); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = ICH_VMCR_EL2(); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = ICH_VMCR_EL2(); end; end; MSR ICH_VMCR_EL2, <Xt> if !(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'1x1'} then NVMem(0x4C8) = X{64}(t); elsif EffectiveHCR_EL2_NVx() IN {'xx1'} then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else ICH_VMCR_EL2() = X{64}(t); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else ICH_VMCR_EL2() = X{64}(t); end; end; 2026-03-26 20:27:25 2026-03_rel