ICH_VTR_EL2 Interrupt Controller VGIC Type Register when GICv3 is implemented, (EL2 is implemented or EL3 is implemented), and FEAT_AA64 is implemented ICH_VTR Architectural AArch32 31 0 31 0 31 0 31 0 Reports supported GIC virtualization features. GIC GIC Host Interface Control Registers Virt Identification Registers If EL2 is not implemented, this register is RES0 from EL3, except for nV4, which is RES1 from EL3. This register has no effect if EL2 is not enabled in the current Security state. ICH_VTR_EL2 is a 64-bit register. 63 32 63:32 Reserved, RES0. PRIbits 31 29 31:29 Priority bits. Indicates the number of virtual priority bits implemented, minus one. An implementation must implement at least 32 levels of virtual priority (5 priority bits). This field is an alias of ICV_CTLR_EL1.PRIbits. 0b100..0b110 The number of virtual priority bits implemented, minus one. RO PREbits 28 26 28:26 Preemption bits. Indicates the number of virtual preemption bits implemented, minus one. An implementation must implement at least 32 levels of virtual preemption priority (5 preemption bits). The value of this field must be less than or equal to the value of ICH_VTR_EL2.PRIbits. This field determines the minimum value of ICH_VMCR_EL2.VBPR0. 0b000..0b110 The number of virtual preemption bits implemented, minus one. RO IDbits 25 23 25:23 The number of virtual interrupt identifier bits supported: All other values are reserved. This field is an alias of ICV_CTLR_EL1.IDbits. 0b000 16 bits. 0b001 24 bits. RO SEIS 22 22 22 SEI Support. Indicates whether the virtual CPU interface supports generation of SEIs: This bit is an alias of ICV_CTLR_EL1.SEIS. 0b0 The virtual CPU interface logic does not support generation of SEIs. 0b1 The virtual CPU interface logic supports generation of SEIs. RO A3V 21 21 21 Affinity 3 Valid. This bit is an alias of ICV_CTLR_EL1.A3V. 0b0 The virtual CPU interface logic only supports zero values of Affinity 3 in SGI generation System registers. 0b1 The virtual CPU interface logic supports nonzero values of Affinity 3 in SGI generation System registers. RO nV4 20 20 20 Direct injection of virtual interrupts not supported. In GICv3, the only permitted value is 1. 0b0 The CPU interface logic supports direct injection of virtual interrupts. 0b1 The CPU interface logic does not support direct injection of virtual interrupts. RO TDS 19 19 0 Separate trapping of EL1 writes to ICV_DIR_EL1 supported. FEAT_GICv3_TDIR implements the functionality added by the value 1. 0b0 Implementation does not support ICH_HCR_EL2.TDIR. 0b1 Implementation supports ICH_HCR_EL2.TDIR. RO When FEAT_GICv3_TDIR is implemented 19 19 19 Reserved, RES0. Otherwise DVIM 18 18 18 Masking of directly-injected virtual interrupts. When a PE implements the Realm Management Extension, this field is RAO/WI. 0b0 Masking of Directly-injected Virtual Interrupts not supported. 0b1 Masking of Directly-injected Virtual Interrupts is supported. RO 17 5 17:5 Reserved, RES0. ListRegs 4 0 4:0 List Registers. Indicates the number of List registers implemented, minus one. 0b00000..0b01111 The number of List registers implemented, minus one. RO MRS <Xt>, ICH_VTR_EL2 if !(IsFeatureImplemented(FEAT_GICv3) && (HaveEL(EL2) || HaveEL(EL3)) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if EffectiveHCR_EL2_NVx() IN {'xx1'} && IsFeatureImplemented(FEAT_GICv3) then AArch64_SystemAccessTrap(EL2, 0x18); else Undefined(); end; elsif PSTATE.EL == EL2 then if ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); else X{64}(t) = ICH_VTR_EL2(); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else X{64}(t) = ICH_VTR_EL2(); end; end; 2026-03-26 20:27:25 2026-03_rel