ICV_AP1R<n>_EL1 Interrupt Controller Virtual Active Priorities Group 1 Registers when GICv3 is implemented, EL2 is implemented, and FEAT_AA64 is implemented 0 3 ICV_AP1R<n> Architectural AArch32 31 0 31 0 31 0 31 0 Provides information about virtual Group 1 active priorities. GICV Control GIC ICV_AP1R<n>_EL1 is a 64-bit register. NMI 63 63 0 Indicates whether the running priority is from a NMI. 0b0 There is no active Group 1 NMI, or all active Group 1 NMIs have undergone priority-drop. 0b1 There is an active Group 1 NMI. '0' When FEAT_GICv3_NMI is implemented and n == 0 63 63 63 Reserved, RES0. Otherwise 62 32 62:32 Reserved, RES0. IMPLEMENTATION DEFINED 31 0 31:0 IMPLEMENTATION DEFINED. AU The contents of these registers are IMPLEMENTATION DEFINED with the one architectural requirement that the value 0x00000000 is consistent with no interrupts being active. Writing to these registers with any value other than the last read value of the register (or 0x00000000 when there are no Group 1 active priorities) might result in UNPREDICTABLE behavior of the virtual interrupt prioritization system, causing: Interrupts that should preempt execution to not preempt execution. Interrupts that should not preempt execution to preempt execution. ICV_AP1R1_EL1 is implemented only in implementations that support 6 or more bits of priority. ICV_AP1R2_EL1 and ICV_AP1R3_EL1 are implemented only in implementations that support 7 bits of priority. Unimplemented registers are UNDEFINED. Writing to the active priority registers in any order other than the following order might result in UNPREDICTABLE behavior of the interrupt prioritization system: ICV_AP0R<n>_EL1. ICV_AP1R<n>_EL1. 0-3 MRS <Xt>, ICC_AP1R<m>_EL1 let m:integer = UInt(op2[1:0]); if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif m == 1 && NUM_GIC_PRIORITY_BITS < 6 then Undefined(); elsif (m == 2 || m == 3) && NUM_GIC_PRIORITY_BITS < 7 then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().IRQ == '1' then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TALL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then X{64}(t) = ICV_AP1R_EL1(m); elsif HaveEL(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_AP1R_EL1_S(m); else X{64}(t) = ICC_AP1R_EL1_NS(m); end; else X{64}(t) = ICC_AP1R_EL1(m); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().IRQ == '1' then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_AP1R_EL1_S(m); else X{64}(t) = ICC_AP1R_EL1_NS(m); end; else X{64}(t) = ICC_AP1R_EL1(m); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_AP1R_EL1_S(m); else X{64}(t) = ICC_AP1R_EL1_NS(m); end; end; end; 0-3 MSR ICC_AP1R<m>_EL1, <Xt> let m:integer = UInt(op2[1:0]); if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif m == 1 && NUM_GIC_PRIORITY_BITS < 6 then Undefined(); elsif (m == 2 || m == 3) && NUM_GIC_PRIORITY_BITS < 7 then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().IRQ == '1' then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TALL1 == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().IMO == '1' then ICV_AP1R_EL1(m) = X{64}(t); elsif HaveEL(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_AP1R_EL1_S(m) = X{64}(t); else ICC_AP1R_EL1_NS(m) = X{64}(t); end; else ICC_AP1R_EL1(m) = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().IRQ == '1' then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().IRQ == '1' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_AP1R_EL1_S(m) = X{64}(t); else ICC_AP1R_EL1_NS(m) = X{64}(t); end; else ICC_AP1R_EL1(m) = X{64}(t); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else if EffectiveSCR_EL3_NS() == '0' then ICC_AP1R_EL1_S(m) = X{64}(t); else ICC_AP1R_EL1_NS(m) = X{64}(t); end; end; end; 2026-03-26 20:27:25 2026-03_rel