ICV_CTLR_EL1 Interrupt Controller Virtual Control Register when GICv3 is implemented, EL2 is implemented, and FEAT_AA64 is implemented ICV_CTLR Architectural AArch32 31 0 31 0 31 0 31 0 Controls aspects of the behavior of the GIC virtual CPU interface and provides information about the features implemented. GICV Control GIC ICV_CTLR_EL1 is a 64-bit register. 63 20 63:20 Reserved, RES0. ExtRange 19 19 19 Extended INTID range (read-only). ICV_CTLR_EL1.ExtRange is an alias of ICC_CTLR_EL1.ExtRange. 0b0 CPU interface does not support INTIDs in the range 1024..8191. Behavior is UNPREDICTABLE if the IRI delivers an interrupt in the range 1024 to 8191 to the CPU interface. Arm strongly recommends that the IRI is not configured to deliver interrupts in this range to a PE that does not support them. 0b1 CPU interface supports INTIDs in the range 1024..8191 All INTIDs in the range 1024..8191 are treated as requiring deactivation. RO RSS 18 18 18 Range Selector Support. This bit is read-only. 0b0 Targeted SGIs with affinity level 0 values of 0 - 15 are supported. 0b1 Targeted SGIs with affinity level 0 values of 0 - 255 are supported. RO 17 16 17:16 Reserved, RES0. A3V 15 15 15 Affinity 3 Valid. Read-only and writes are ignored. 0b0 The virtual CPU interface logic only supports zero values of Affinity 3 in SGI generation System registers. 0b1 The virtual CPU interface logic supports nonzero values of Affinity 3 in SGI generation System registers. RO SEIS 14 14 14 SEI Support. Read-only and writes are ignored. Indicates whether the virtual CPU interface supports local generation of SEIs. 0b0 The virtual CPU interface logic does not support local generation of SEIs. 0b1 The virtual CPU interface logic supports local generation of SEIs. RO IDbits 13 11 13:11 Identifier bits. Read-only and writes are ignored. Indicates the number of virtual interrupt identifier bits supported. All other values are reserved. 0b000 16 bits. 0b001 24 bits. RO PRIbits 10 8 10:8 Indicates the number of virtual priority bits implemented. An implementation must implement at least 32 levels of virtual priority (5 priority bits). The division between group priority and subpriority is defined in the binary point registers ICV_BPR0_EL1 and ICV_BPR1_EL1. 0b100..0b110 The number of virtual priority bits implemented, minus one. RO 7 2 7:2 Reserved, RES0. EOImode 1 1 1 Virtual EOI mode. Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt: 0b0 ICV_EOIR0_EL1 and ICV_EOIR1_EL1 provide both priority drop and interrupt deactivation functionality. Accesses to ICV_DIR_EL1 are UNPREDICTABLE. 0b1 ICV_EOIR0_EL1 and ICV_EOIR1_EL1 provide priority drop functionality only. ICV_DIR_EL1 provides interrupt deactivation functionality. AU CBPR 0 0 0 Common Binary Point Register. Controls whether the same register is used for interrupt preemption of both virtual Group 0 and virtual Group 1 interrupts: 0b0 ICV_BPR1_EL1 determines the preemption group for virtual Group 1 interrupts. 0b1 Non-secure reads of ICV_BPR1_EL1 return ICV_BPR0_EL1 plus one, saturated to 0b111. Non-secure writes to ICV_BPR1_EL1 are ignored. Secure reads of ICV_BPR1_EL1 return ICV_BPR0_EL1. Secure writes of ICV_BPR1_EL1 modify ICV_BPR0_EL1. AU MRS <Xt>, ICC_CTLR_EL1 if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().FMO == '1' then X{64}(t) = ICV_CTLR_EL1(); elsif EL2Enabled() && HCR_EL2().IMO == '1' then X{64}(t) = ICV_CTLR_EL1(); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_CTLR_EL1_S(); else X{64}(t) = ICC_CTLR_EL1_NS(); end; else X{64}(t) = ICC_CTLR_EL1(); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_CTLR_EL1_S(); else X{64}(t) = ICC_CTLR_EL1_NS(); end; else X{64}(t) = ICC_CTLR_EL1(); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else if EffectiveSCR_EL3_NS() == '0' then X{64}(t) = ICC_CTLR_EL1_S(); else X{64}(t) = ICC_CTLR_EL1_NS(); end; end; end; MSR ICC_CTLR_EL1, <Xt> if !(IsFeatureImplemented(FEAT_GICv3) && IsFeatureImplemented(FEAT_AA64)) then Undefined(); elsif PSTATE.EL == EL0 then Undefined(); elsif PSTATE.EL == EL1 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif ICC_SRE_EL1().SRE == '0' then AArch64_SystemAccessTrap(EL1, 0x18); elsif EL2Enabled() && ICH_HCR_EL2().TC == '1' then AArch64_SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2().FMO == '1' then ICV_CTLR_EL1() = X{64}(t); elsif EL2Enabled() && HCR_EL2().IMO == '1' then ICV_CTLR_EL1() = X{64}(t); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_CTLR_EL1_S() = X{64}(t); else ICC_CTLR_EL1_NS() = X{64}(t); end; else ICC_CTLR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL2 then if HaveEL(EL3) && EL3SDDUndefPriority() && SCR_EL3().[IRQ,FIQ] == '11' then Undefined(); elsif ICC_SRE_EL2().SRE == '0' then AArch64_SystemAccessTrap(EL2, 0x18); elsif HaveEL(EL3) && SCR_EL3().[IRQ,FIQ] == '11' then if EL3SDDUndef() then Undefined(); else AArch64_SystemAccessTrap(EL3, 0x18); end; elsif HaveEL(EL3) then if EffectiveSCR_EL3_NS() == '0' then ICC_CTLR_EL1_S() = X{64}(t); else ICC_CTLR_EL1_NS() = X{64}(t); end; else ICC_CTLR_EL1() = X{64}(t); end; elsif PSTATE.EL == EL3 then if ICC_SRE_EL3().SRE == '0' then AArch64_SystemAccessTrap(EL3, 0x18); else if EffectiveSCR_EL3_NS() == '0' then ICC_CTLR_EL1_S() = X{64}(t); else ICC_CTLR_EL1_NS() = X{64}(t); end; end; end; 2026-03-26 20:27:25 2026-03_rel